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authormergify[bot]2022-06-02 18:06:03 +0000
committerGitHub2022-06-02 18:06:03 +0000
commit5bec54e535dca53c9347caddb0b395c4651a0919 (patch)
treeea9b4e534b19be7385a14d00ab434f23b54f648f /src/test/scala/chiselTests/VerificationSpec.scala
parent97fde23f666a560d4eba9333e4230f901d7f5361 (diff)
Support VerificationStatement in the naming plugin (#2555) (#2557)
Previously, verification statements (assert, assume, cover, and printf) were only named via reflection. (cherry picked from commit 7fa2691f670813eef4ec59fc27c4e4f625d598de) Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/VerificationSpec.scala')
-rw-r--r--src/test/scala/chiselTests/VerificationSpec.scala10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/VerificationSpec.scala b/src/test/scala/chiselTests/VerificationSpec.scala
index 95b0ffe6..32cee9e3 100644
--- a/src/test/scala/chiselTests/VerificationSpec.scala
+++ b/src/test/scala/chiselTests/VerificationSpec.scala
@@ -105,9 +105,9 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
val firLines = scala.io.Source.fromFile(firFile).getLines.toList
// check that verification components have expected names
- exactly(1, firLines) should include("cover(clock, _T, UInt<1>(\"h1\"), \"\") : cov")
- exactly(1, firLines) should include("assume(clock, _T_3, UInt<1>(\"h1\"), \"\") : assm")
- exactly(1, firLines) should include("assert(clock, _T_7, UInt<1>(\"h1\"), \"\") : asst")
+ (exactly(1, firLines) should include).regex("^\\s*cover\\(.*\\) : cov")
+ (exactly(1, firLines) should include).regex("^\\s*assume\\(.*\\) : assm")
+ (exactly(1, firLines) should include).regex("^\\s*assert\\(.*\\) : asst")
}
property("annotation of verification constructs with suggested name should work") {
@@ -150,7 +150,7 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
val firLines = scala.io.Source.fromFile(firFile).getLines.toList
// check that verification components have expected names
- exactly(1, firLines) should include("assert(clock, _T, UInt<1>(\"h1\"), \"\") : hello")
- exactly(1, firLines) should include("assume(clock, _T_4, UInt<1>(\"h1\"), \"\") : howdy")
+ (exactly(1, firLines) should include).regex("^\\s*assert\\(.*\\) : hello")
+ (exactly(1, firLines) should include).regex("^\\s*assume\\(.*\\) : howdy")
}
}