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authormergify[bot]2022-06-02 18:06:03 +0000
committerGitHub2022-06-02 18:06:03 +0000
commit5bec54e535dca53c9347caddb0b395c4651a0919 (patch)
treeea9b4e534b19be7385a14d00ab434f23b54f648f /src
parent97fde23f666a560d4eba9333e4230f901d7f5361 (diff)
Support VerificationStatement in the naming plugin (#2555) (#2557)
Previously, verification statements (assert, assume, cover, and printf) were only named via reflection. (cherry picked from commit 7fa2691f670813eef4ec59fc27c4e4f625d598de) Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/chiselTests/VerificationSpec.scala10
-rw-r--r--src/test/scala/chiselTests/naming/NamePluginSpec.scala19
-rw-r--r--src/test/scala/chiselTests/naming/PrefixSpec.scala21
3 files changed, 45 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/VerificationSpec.scala b/src/test/scala/chiselTests/VerificationSpec.scala
index 95b0ffe6..32cee9e3 100644
--- a/src/test/scala/chiselTests/VerificationSpec.scala
+++ b/src/test/scala/chiselTests/VerificationSpec.scala
@@ -105,9 +105,9 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
val firLines = scala.io.Source.fromFile(firFile).getLines.toList
// check that verification components have expected names
- exactly(1, firLines) should include("cover(clock, _T, UInt<1>(\"h1\"), \"\") : cov")
- exactly(1, firLines) should include("assume(clock, _T_3, UInt<1>(\"h1\"), \"\") : assm")
- exactly(1, firLines) should include("assert(clock, _T_7, UInt<1>(\"h1\"), \"\") : asst")
+ (exactly(1, firLines) should include).regex("^\\s*cover\\(.*\\) : cov")
+ (exactly(1, firLines) should include).regex("^\\s*assume\\(.*\\) : assm")
+ (exactly(1, firLines) should include).regex("^\\s*assert\\(.*\\) : asst")
}
property("annotation of verification constructs with suggested name should work") {
@@ -150,7 +150,7 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
val firLines = scala.io.Source.fromFile(firFile).getLines.toList
// check that verification components have expected names
- exactly(1, firLines) should include("assert(clock, _T, UInt<1>(\"h1\"), \"\") : hello")
- exactly(1, firLines) should include("assume(clock, _T_4, UInt<1>(\"h1\"), \"\") : howdy")
+ (exactly(1, firLines) should include).regex("^\\s*assert\\(.*\\) : hello")
+ (exactly(1, firLines) should include).regex("^\\s*assume\\(.*\\) : howdy")
}
}
diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 18359fd2..482ef62b 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -3,6 +3,7 @@
package chiselTests.naming
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.aop.Select
import chisel3.experimental.{prefix, treedump}
import chiselTests.{ChiselFlatSpec, Utils}
@@ -69,6 +70,24 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
}
}
+ "Scala plugin" should "name verification ops" in {
+ class Test extends Module {
+ val foo, bar = IO(Input(UInt(8.W)))
+
+ {
+ val x1 = chisel3.assert(1.U === 1.U)
+ val x2 = cover(foo =/= bar)
+ val x3 = chisel3.assume(foo =/= 123.U)
+ val x4 = printf("foo = %d\n", foo)
+ }
+ }
+ val chirrtl = ChiselStage.emitChirrtl(new Test)
+ (chirrtl should include).regex("assert.*: x1")
+ (chirrtl should include).regex("cover.*: x2")
+ (chirrtl should include).regex("assume.*: x3")
+ (chirrtl should include).regex("printf.*: x4")
+ }
+
"Naming on option" should "work" in {
class Test extends Module {
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index f9a78f0e..1e628391 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -3,6 +3,7 @@
package chiselTests.naming
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.aop.Select
import chisel3.experimental.{dump, noPrefix, prefix, treedump}
import chiselTests.{ChiselPropSpec, Utils}
@@ -391,6 +392,26 @@ class PrefixSpec extends ChiselPropSpec with Utils {
aspectTest(() => new Test) { top: Test =>
Select.wires(top).map(_.instanceName) should be(List("x", "x_w_w", "x_w_w_w", "x_w_w_w_w"))
}
+ }
+
+ property("Prefixing should work for verification ops") {
+ class Test extends Module {
+ val foo, bar = IO(Input(UInt(8.W)))
+ {
+ val x5 = {
+ val x1 = chisel3.assert(1.U === 1.U)
+ val x2 = cover(foo =/= bar)
+ val x3 = chisel3.assume(foo =/= 123.U)
+ val x4 = printf("foo = %d\n", foo)
+ x1
+ }
+ }
+ }
+ val chirrtl = ChiselStage.emitChirrtl(new Test)
+ (chirrtl should include).regex("assert.*: x5")
+ (chirrtl should include).regex("cover.*: x5_x2")
+ (chirrtl should include).regex("assume.*: x5_x3")
+ (chirrtl should include).regex("printf.*: x5_x4")
}
}