summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--plugin/src/main/scala/chisel3/internal/plugin/ChiselComponent.scala13
-rw-r--r--src/test/scala/chiselTests/VerificationSpec.scala10
-rw-r--r--src/test/scala/chiselTests/naming/NamePluginSpec.scala19
-rw-r--r--src/test/scala/chiselTests/naming/PrefixSpec.scala21
4 files changed, 53 insertions, 10 deletions
diff --git a/plugin/src/main/scala/chisel3/internal/plugin/ChiselComponent.scala b/plugin/src/main/scala/chisel3/internal/plugin/ChiselComponent.scala
index eced652b..f98049e2 100644
--- a/plugin/src/main/scala/chisel3/internal/plugin/ChiselComponent.scala
+++ b/plugin/src/main/scala/chisel3/internal/plugin/ChiselComponent.scala
@@ -78,10 +78,13 @@ class ChiselComponent(val global: Global, arguments: ChiselPluginArguments)
}
}
- private val shouldMatchData: Type => Boolean = shouldMatchGen(tq"chisel3.Data")
- private val shouldMatchDataOrMem: Type => Boolean = shouldMatchGen(tq"chisel3.Data", tq"chisel3.MemBase[_]")
- private val shouldMatchModule: Type => Boolean = shouldMatchGen(tq"chisel3.experimental.BaseModule")
- private val shouldMatchInstance: Type => Boolean = shouldMatchGen(tq"chisel3.experimental.hierarchy.Instance[_]")
+ private val shouldMatchData: Type => Boolean = shouldMatchGen(tq"chisel3.Data")
+ // Checking for all chisel3.internal.NamedComponents, but since it is internal, we instead have
+ // to match the public subtypes
+ private val shouldMatchNamedComp: Type => Boolean =
+ shouldMatchGen(tq"chisel3.Data", tq"chisel3.MemBase[_]", tq"chisel3.VerificationStatement")
+ private val shouldMatchModule: Type => Boolean = shouldMatchGen(tq"chisel3.experimental.BaseModule")
+ private val shouldMatchInstance: Type => Boolean = shouldMatchGen(tq"chisel3.experimental.hierarchy.Instance[_]")
// Given a type tree, infer the type and return it
private def inferType(t: Tree): Type = localTyper.typed(t, nsc.Mode.TYPEmode).tpe
@@ -176,7 +179,7 @@ class ChiselComponent(val global: Global, arguments: ChiselPluginArguments)
treeCopy.ValDef(dd, mods, name, tpt, localTyper.typed(named))
}
// If a Data or a Memory, get the name and a prefix
- else if (shouldMatchDataOrMem(tpe)) {
+ else if (shouldMatchNamedComp(tpe)) {
val str = stringFromTermName(name)
val newRHS = transform(rhs)
val prefixed = q"chisel3.experimental.prefix.apply[$tpt](name=$str)(f=$newRHS)"
diff --git a/src/test/scala/chiselTests/VerificationSpec.scala b/src/test/scala/chiselTests/VerificationSpec.scala
index 95b0ffe6..32cee9e3 100644
--- a/src/test/scala/chiselTests/VerificationSpec.scala
+++ b/src/test/scala/chiselTests/VerificationSpec.scala
@@ -105,9 +105,9 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
val firLines = scala.io.Source.fromFile(firFile).getLines.toList
// check that verification components have expected names
- exactly(1, firLines) should include("cover(clock, _T, UInt<1>(\"h1\"), \"\") : cov")
- exactly(1, firLines) should include("assume(clock, _T_3, UInt<1>(\"h1\"), \"\") : assm")
- exactly(1, firLines) should include("assert(clock, _T_7, UInt<1>(\"h1\"), \"\") : asst")
+ (exactly(1, firLines) should include).regex("^\\s*cover\\(.*\\) : cov")
+ (exactly(1, firLines) should include).regex("^\\s*assume\\(.*\\) : assm")
+ (exactly(1, firLines) should include).regex("^\\s*assert\\(.*\\) : asst")
}
property("annotation of verification constructs with suggested name should work") {
@@ -150,7 +150,7 @@ class VerificationSpec extends ChiselPropSpec with Matchers {
val firLines = scala.io.Source.fromFile(firFile).getLines.toList
// check that verification components have expected names
- exactly(1, firLines) should include("assert(clock, _T, UInt<1>(\"h1\"), \"\") : hello")
- exactly(1, firLines) should include("assume(clock, _T_4, UInt<1>(\"h1\"), \"\") : howdy")
+ (exactly(1, firLines) should include).regex("^\\s*assert\\(.*\\) : hello")
+ (exactly(1, firLines) should include).regex("^\\s*assume\\(.*\\) : howdy")
}
}
diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index 18359fd2..482ef62b 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -3,6 +3,7 @@
package chiselTests.naming
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.aop.Select
import chisel3.experimental.{prefix, treedump}
import chiselTests.{ChiselFlatSpec, Utils}
@@ -69,6 +70,24 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
}
}
+ "Scala plugin" should "name verification ops" in {
+ class Test extends Module {
+ val foo, bar = IO(Input(UInt(8.W)))
+
+ {
+ val x1 = chisel3.assert(1.U === 1.U)
+ val x2 = cover(foo =/= bar)
+ val x3 = chisel3.assume(foo =/= 123.U)
+ val x4 = printf("foo = %d\n", foo)
+ }
+ }
+ val chirrtl = ChiselStage.emitChirrtl(new Test)
+ (chirrtl should include).regex("assert.*: x1")
+ (chirrtl should include).regex("cover.*: x2")
+ (chirrtl should include).regex("assume.*: x3")
+ (chirrtl should include).regex("printf.*: x4")
+ }
+
"Naming on option" should "work" in {
class Test extends Module {
diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index f9a78f0e..1e628391 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -3,6 +3,7 @@
package chiselTests.naming
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.aop.Select
import chisel3.experimental.{dump, noPrefix, prefix, treedump}
import chiselTests.{ChiselPropSpec, Utils}
@@ -391,6 +392,26 @@ class PrefixSpec extends ChiselPropSpec with Utils {
aspectTest(() => new Test) { top: Test =>
Select.wires(top).map(_.instanceName) should be(List("x", "x_w_w", "x_w_w_w", "x_w_w_w_w"))
}
+ }
+
+ property("Prefixing should work for verification ops") {
+ class Test extends Module {
+ val foo, bar = IO(Input(UInt(8.W)))
+ {
+ val x5 = {
+ val x1 = chisel3.assert(1.U === 1.U)
+ val x2 = cover(foo =/= bar)
+ val x3 = chisel3.assume(foo =/= 123.U)
+ val x4 = printf("foo = %d\n", foo)
+ x1
+ }
+ }
+ }
+ val chirrtl = ChiselStage.emitChirrtl(new Test)
+ (chirrtl should include).regex("assert.*: x5")
+ (chirrtl should include).regex("cover.*: x5_x2")
+ (chirrtl should include).regex("assume.*: x5_x3")
+ (chirrtl should include).regex("printf.*: x5_x4")
}
}