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authorMartin Schoeberl2019-01-25 23:24:01 -0800
committerRichard Lin2019-01-25 23:24:01 -0800
commit5509cdd4c8332c53151e10ba5bdbe0684af1c05b (patch)
tree15f4a7e8f83e0d249918bbce4198160fb2c5360f /src/test/scala/chiselTests/TesterDriverSpec.scala
parent4f5ec211cb59f9da37dbe91d0dfcb93c4d3d84c9 (diff)
WireDefault instead of WireInit, keep WireInit around (#986)
Diffstat (limited to 'src/test/scala/chiselTests/TesterDriverSpec.scala')
-rw-r--r--src/test/scala/chiselTests/TesterDriverSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index f3cf3bca..a7137699 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -21,7 +21,7 @@ class FinishTester extends BasicTester {
stop()
}
- val test_wire = WireInit(1.U(test_wire_width.W))
+ val test_wire = WireDefault(1.U(test_wire_width.W))
// though we just set test_wire to 1, the assert below will pass because
// the finish will change its value