diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/test/scala/chiselTests/Stack.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index df1e68bf..3cdb68eb 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -17,8 +17,8 @@ class ChiselStack(val depth: Int) extends Module { }) val stack_mem = Mem(depth, UInt(32.W)) - val sp = Reg(init = 0.U(log2Ceil(depth+1).W)) - val out = Reg(init = 0.U(32.W)) + val sp = RegInit(0.U(log2Ceil(depth+1).W)) + val out = RegInit(0.U(32.W)) when (io.en) { when(io.push && (sp < depth.asUInt)) { |
