diff options
| author | Jim Lawson | 2019-03-18 12:17:33 -0700 |
|---|---|---|
| committer | GitHub | 2019-03-18 12:17:33 -0700 |
| commit | 2c449c5d6e23dcbb60e8c64cab6b6f4ba6ae313f (patch) | |
| tree | 3daffa8eb0f57faf31d3977700be38f5be31e59a /src/test/scala/chiselTests/Stack.scala | |
| parent | cfb2f08db9d9df121a82f138dd71297dbcea66cc (diff) | |
Split #974 into two PRs - scalastyle updates (#1037)
* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
* Remove bogus tests that crept in with git add
* Add missing import.
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 3cdb68eb..9f17c741 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module { }) val stack_mem = Mem(depth, UInt(32.W)) - val sp = RegInit(0.U(log2Ceil(depth+1).W)) + val sp = RegInit(0.U(log2Ceil(depth + 1).W)) val out = RegInit(0.U(32.W)) when (io.en) { |