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| author | ducky | 2018-01-19 19:19:43 -0800 |
|---|---|---|
| committer | Richard Lin | 2018-01-19 21:39:36 -0800 |
| commit | 70ca35b9d7b3884e5f701d49bc5286f89701fd14 (patch) | |
| tree | 018a4d886b146e326c7dbabf51056a71dd6ccd7d /src/test/scala/chiselTests/MemorySearch.scala | |
| parent | 6b277ff0c3266e9b02fe9b483086ab46085202ce (diff) | |
Fix deprecations in tests
Diffstat (limited to 'src/test/scala/chiselTests/MemorySearch.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MemorySearch.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index d36167a4..93902d22 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -14,7 +14,7 @@ class MemorySearch extends Module { }) val vals = Array(0, 4, 15, 14, 2, 5, 13) val index = RegInit(0.U(3.W)) - val elts = Vec(vals.map(_.asUInt(4.W))) + val elts = VecInit(vals.map(_.asUInt(4.W))) // val elts = Mem(UInt(32.W), 8) TODO ???? val elt = elts(index) val end = !io.en && ((elt === io.target) || (index === 7.U)) |
