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| author | Jim Lawson | 2016-07-20 14:49:35 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-20 14:49:35 -0700 |
| commit | 2dce378deda1cc33833eb378c89a1c5415817bae (patch) | |
| tree | e3bc5361030d63e017d065491e9e7e4cf788fe3c /src/test/scala/chiselTests/LFSR16.scala | |
| parent | 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff) | |
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'src/test/scala/chiselTests/LFSR16.scala')
| -rw-r--r-- | src/test/scala/chiselTests/LFSR16.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index 2d5e7f3e..b13b67e3 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -9,7 +9,7 @@ import chisel3.util._ class LFSR16 extends Module { val io = IO(new Bundle { val inc = Input(Bool()) - val out = Output(UInt(16)) + val out = Output(UInt.width(16)) }) val res = Reg(init = UInt(1, 16)) when (io.inc) { |