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| author | Richard Lin | 2018-10-03 16:15:37 -0700 |
|---|---|---|
| committer | GitHub | 2018-10-03 16:15:37 -0700 |
| commit | dafdeab614a5106dac4d80e147fdbc2770053e1b (patch) | |
| tree | efd4ae2f9b612e55c87227851813afb6644ddd3a /src/test/scala/chiselTests/ExtModule.scala | |
| parent | b87e6cf65920832c5a0d908b9862edcccf5cae5d (diff) | |
Add DataMirror.modulePorts (#901)
Diffstat (limited to 'src/test/scala/chiselTests/ExtModule.scala')
| -rw-r--r-- | src/test/scala/chiselTests/ExtModule.scala | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala index 6bffa333..5d5b51f9 100644 --- a/src/test/scala/chiselTests/ExtModule.scala +++ b/src/test/scala/chiselTests/ExtModule.scala @@ -68,4 +68,12 @@ class ExtModuleSpec extends ChiselFlatSpec { assertTesterPasses({ new MultiExtModuleTester }, Seq("/chisel3/BlackBoxTest.v")) } + "DataMirror.modulePorts" should "work with ExtModule" in { + elaborate(new Module { + val io = IO(new Bundle { }) + val m = Module(new ExtModule.BlackBoxPassthrough) + assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + "in" -> m.in, "out" -> m.out)) + }) + } } |
