Add DataMirror.modulePorts (#901)

3 files changed, 28 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 27895a54..b45171f4 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -172,4 +172,12 @@ class BlackBoxSpec extends ChiselFlatSpec {
     assertTesterPasses({ new BlackBoxWithParamsTester },
         Seq("/chisel3/BlackBoxTest.v"))
   }
+  "DataMirror.modulePorts" should "work with BlackBox" in {
+    elaborate(new Module {
+      val io = IO(new Bundle { })
+      val m = Module(new BlackBoxPassthrough)
+      assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq(
+          "in" -> m.io.in, "out" -> m.io.out))
+    })
+  }
 }
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index 6bffa333..5d5b51f9 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -68,4 +68,12 @@ class ExtModuleSpec extends ChiselFlatSpec {
     assertTesterPasses({ new MultiExtModuleTester },
         Seq("/chisel3/BlackBoxTest.v"))
   }
+  "DataMirror.modulePorts" should "work with ExtModule" in {
+    elaborate(new Module {
+      val io = IO(new Bundle { })
+      val m = Module(new ExtModule.BlackBoxPassthrough)
+      assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq(
+          "in" -> m.in, "out" -> m.out))
+    })
+  }
 }
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 5f2927dd..968e7578 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -126,4 +126,16 @@ class ModuleSpec extends ChiselPropSpec {
       assert(checkModule(this))
     })
   }
+  property("DataMirror.modulePorts should work") {
+    elaborate(new Module {
+      val io = IO(new Bundle { })
+      val m = Module(new chisel3.experimental.MultiIOModule {
+        val a = IO(UInt(8.W))
+        val b = IO(Bool())
+      })
+      assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq(
+          "clock" -> m.clock, "reset" -> m.reset,
+          "a" -> m.a, "b" -> m.b))
+    })
+  }
 }