From dafdeab614a5106dac4d80e147fdbc2770053e1b Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 3 Oct 2018 16:15:37 -0700
Subject: Add DataMirror.modulePorts (#901)

---
 src/test/scala/chiselTests/ExtModule.scala | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/test/scala/chiselTests/ExtModule.scala')

diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index 6bffa333..5d5b51f9 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -68,4 +68,12 @@ class ExtModuleSpec extends ChiselFlatSpec {
     assertTesterPasses({ new MultiExtModuleTester },
         Seq("/chisel3/BlackBoxTest.v"))
   }
+  "DataMirror.modulePorts" should "work with ExtModule" in {
+    elaborate(new Module {
+      val io = IO(new Bundle { })
+      val m = Module(new ExtModule.BlackBoxPassthrough)
+      assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq(
+          "in" -> m.in, "out" -> m.out))
+    })
+  }
 }
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