diff options
| author | Jack Koenig | 2019-09-13 10:05:57 -0700 |
|---|---|---|
| committer | GitHub | 2019-09-13 10:05:57 -0700 |
| commit | 14503966b017d160e46cc7e401c2ffa2c39212e8 (patch) | |
| tree | d9c16ac797765a090059f3781fb991422f2c2c92 /src/test/scala/chiselTests/CompatibilitySpec.scala | |
| parent | 3d65ccee36fd97c26d170f631322ad0c2c9d6dd7 (diff) | |
Fix Queue.apply for size 0 in chisel3._ code (#1177)
Diffstat (limited to 'src/test/scala/chiselTests/CompatibilitySpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index c602efa3..d2b39c49 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -97,6 +97,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks val dcd = Wire(Decoupled(data)) dcd shouldBe a [DecoupledIO[UInt]] Queue(dcd) shouldBe a [DecoupledIO[UInt]] + Queue(dcd, 0) shouldBe a [DecoupledIO[UInt]] Enum(UInt(), 2) shouldBe a [List[UInt]] ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]] Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt] |