From 14503966b017d160e46cc7e401c2ffa2c39212e8 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 13 Sep 2019 10:05:57 -0700
Subject: Fix Queue.apply for size 0 in chisel3._ code (#1177)

---
 src/test/scala/chiselTests/CompatibilitySpec.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/test/scala/chiselTests/CompatibilitySpec.scala')

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index c602efa3..d2b39c49 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -97,6 +97,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
       val dcd = Wire(Decoupled(data))
       dcd shouldBe a [DecoupledIO[UInt]]
       Queue(dcd) shouldBe a [DecoupledIO[UInt]]
+      Queue(dcd, 0) shouldBe a [DecoupledIO[UInt]]
       Enum(UInt(), 2) shouldBe a [List[UInt]]
       ListLookup(wire, List(wire), Array((BitPat("b1"), List(wire)))) shouldBe a [List[UInt]]
       Lookup(wire, wire, Seq((BitPat("b1"), wire))) shouldBe a [UInt]
-- 
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