diff options
| author | mergify[bot] | 2022-03-10 01:10:30 +0000 |
|---|---|---|
| committer | GitHub | 2022-03-10 01:10:30 +0000 |
| commit | 741761cfbac8d8b7e297666c66d91cb773a6f109 (patch) | |
| tree | ee5c63cd117b8e8bc93ad3383c6d0981f077f6a9 /src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala | |
| parent | 4ee545d7706a2d2ba59902fb86a4393287327a9a (diff) | |
Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)
Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.
Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 8210b120..70dcda48 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -74,7 +74,7 @@ object Chisel3Components { class Chisel3ModuleChiselRecordB extends Chisel3PassthroughModule(Flipped(new ChiselRecord)) } -class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec { +class CompatibilityInteroperabilitySpec extends ChiselFlatSpec { "Modules defined in the Chisel._" should "successfully bulk connect in chisel3._" in { import chisel3._ |