From 741761cfbac8d8b7e297666c66d91cb773a6f109 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Thu, 10 Mar 2022 01:10:30 +0000 Subject: Emit FIRRTL bulkconnects whenever possible (#2381) (#2440) Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung Co-authored-by: Jack Koenig (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig --- src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala') diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 8210b120..70dcda48 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -74,7 +74,7 @@ object Chisel3Components { class Chisel3ModuleChiselRecordB extends Chisel3PassthroughModule(Flipped(new ChiselRecord)) } -class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec { +class CompatibilityInteroperabilitySpec extends ChiselFlatSpec { "Modules defined in the Chisel._" should "successfully bulk connect in chisel3._" in { import chisel3._ -- cgit v1.2.3