Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)

Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

7 files changed, 149 insertions, 8 deletions

diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
new file mode 100644
index 00000000..463122bd
--- /dev/null
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -0,0 +1,106 @@
+package chiselTests
+
+import chisel3._
+import chisel3.util.Decoupled
+import chisel3.stage.ChiselStage
+import chisel3.testers.BasicTester
+
+class BulkConnectSpec extends ChiselPropSpec {
+  property("Chisel connects should emit FIRRTL bulk connects when possible") {
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      val io = IO(new Bundle {
+        val inMono = Input(Vec(4, UInt(8.W)))
+        val outMono = Output(Vec(4, UInt(8.W)))
+        val inBi = Input(Vec(4, UInt(8.W)))
+        val outBi = Output(Vec(4, UInt(8.W)))
+      })
+      io.outMono := io.inMono
+      io.outBi <> io.inBi
+    })
+    chirrtl should include("io.outMono <= io.inMono")
+    chirrtl should include("io.outBi <= io.inBi")
+  }
+
+  property("Chisel connects should not emit FIRRTL bulk connects for Stringly-typed connections") {
+    object Foo {
+      import Chisel._
+      // Chisel._ bundle
+      class BundleParent extends Bundle {
+        val foo = UInt(width = 8)
+      }
+      class BundleChild extends BundleParent {
+        val bar = UInt(width = 8)
+      }
+    }
+
+    import Foo._
+
+    // chisel3._ bundle
+    class MyBundle(child: Boolean) extends Bundle {
+      val fizz = UInt(8.W)
+      val buzz = if (child) new BundleChild else new BundleParent
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      // Checking MonoConnect
+      val in = IO(Input(new MyBundle(true)))
+      val out = IO(Output(new MyBundle(false)))
+      out := in
+
+      // Checking BulkConnect (with Decoupled)
+      val enq = IO(Flipped(Decoupled(new BundleChild)))
+      val deq = IO(Decoupled(new BundleParent))
+      deq <> enq
+    })
+
+    chirrtl should include("out.buzz.foo <= in.buzz.foo")
+    chirrtl shouldNot include("deq <= enq")
+  }
+
+  property("Chisel connects should not emit FIRRTL bulk connects between differing FIRRTL types") {
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      val in = IO(Flipped(new Bundle {
+        val foo = Flipped(new Bundle {
+          val bar = Input(UInt(8.W))
+        })
+      }))
+      val out = IO(Output(new Bundle {
+        val foo = new Bundle {
+          val bar = UInt(8.W)
+        }
+      }))
+      // Both of these connections are legal in Chisel, but in and out do not have the same type
+      out := in
+      out <> in
+    })
+    // out <- in is illegal FIRRTL
+    chirrtl should include("out.foo.bar <= in.foo.bar")
+  }
+
+  property("Chisel connects should not emit a FIRRTL bulk connect for a bidirectional MonoConnect") {
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      val enq = IO(Flipped(Decoupled(UInt(8.W))))
+      val deq = IO(Decoupled(UInt(8.W)))
+
+      // Implicitly create a MonoConnect from enq to a wire
+      // enq is a Decoupled and so has input/output signals
+      // We should not bulk connect in this case
+      val wire = WireDefault(enq)
+      dontTouch(wire)
+      deq <> enq
+    })
+
+    chirrtl shouldNot include("wire <= enq")
+    chirrtl should include("deq <= enq")
+  }
+
+  property("MonoConnect should bulk connect undirectioned internal wires") {
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      val io = IO(new Bundle {})
+      val w1 = Wire(Vec(2, UInt(8.W)))
+      val w2 = Wire(Vec(2, UInt(8.W)))
+      w2 := w1
+    })
+    chirrtl should include("w2 <= w1")
+  }
+}
diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala
index 5dcbbefa..2d34b263 100644
--- a/src/test/scala/chiselTests/BundleSpec.scala
+++ b/src/test/scala/chiselTests/BundleSpec.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.util.Decoupled
 import chisel3.stage.ChiselStage
 import chisel3.testers.BasicTester
 
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 8210b120..70dcda48 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -74,7 +74,7 @@ object Chisel3Components {
   class Chisel3ModuleChiselRecordB extends Chisel3PassthroughModule(Flipped(new ChiselRecord))
 }
 
-class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
+class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "Modules defined in the Chisel._" should "successfully bulk connect in chisel3._" in {
     import chisel3._
diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index 16efafd4..ee19d653 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -280,4 +280,20 @@ class MixedVecSpec extends ChiselPropSpec with Utils {
       })
     }
   }
+
+  property("MixedVec connections should emit FIRRTL bulk connects when possible") {
+    val chirrtl = ChiselStage.emitChirrtl(new Module {
+      val io = IO(new Bundle {
+        val inMono = Input(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+        val outMono = Output(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+        val inBi = Input(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+        val outBi = Output(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W))))
+      })
+      // Explicit upcast avoids weird issue where Scala 2.12 overloading resolution calls version of := accepting Seq[T] instead of normal Data version
+      io.outMono := (io.inMono: Data)
+      io.outBi <> io.inBi
+    })
+    chirrtl should include("io.outMono <= io.inMono @[MixedVecSpec.scala")
+    chirrtl should include("io.outBi <= io.inBi @[MixedVecSpec.scala")
+  }
 }
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index da3840dd..30b55812 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -27,6 +27,17 @@ trait RecordSpecUtils {
     io.out <> io.in
   }
 
+  class ConnectionTestModule(output: => Record, input: => Record) extends Module {
+    val io = IO(new Bundle {
+      val inMono = Input(input)
+      val outMono = Output(output)
+      val inBi = Input(input)
+      val outBi = Output(output)
+    })
+    io.outMono := io.inMono
+    io.outBi <> io.inBi
+  }
+
   class RecordSerializationTest extends BasicTester {
     val recordType = new CustomBundle("fizz" -> UInt(16.W), "buzz" -> UInt(16.W))
     val record = Wire(recordType)
@@ -110,6 +121,14 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     ChiselStage.elaborate { new MyModule(new MyBundle, fooBarType) }
   }
 
+  they should "emit FIRRTL bulk connects when possible" in {
+    val chirrtl = (new ChiselStage).emitChirrtl(
+      gen = new ConnectionTestModule(fooBarType, fooBarType)
+    )
+    chirrtl should include("io.outMono <= io.inMono @[RecordSpec.scala")
+    chirrtl should include("io.outBi <= io.inBi @[RecordSpec.scala")
+  }
+
   they should "not allow aliased fields" in {
     class AliasedFieldRecord extends Record {
       val foo = UInt(8.W)
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index 228f409b..fa97a8c8 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -434,7 +434,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
     exc.getMessage should include("field 0 specified with non-literal value UInt")
   }
 
-  "vec literals are instantiated on connect" in {
+  "vec literals are instantiated on connect and are not bulk connected" in {
     class VecExample5 extends RawModule {
       val out = IO(Output(Vec(2, UInt(4.W))))
       val bundle = Vec(2, UInt(4.W)).Lit(
@@ -463,13 +463,12 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
     out := bundle
   }
 
-  "vec literals can contain bundles" in {
+  "vec literals can contain bundles and should not be bulk connected" in {
     val chirrtl = (new chisel3.stage.ChiselStage).emitChirrtl(new VecExample, args = Array("--full-stacktrace"))
     chirrtl should include("""out[0].bar <= UInt<5>("h16")""")
     chirrtl should include("""out[0].foo <= UInt<6>("h2a")""")
     chirrtl should include("""out[1].bar <= UInt<2>("h3")""")
     chirrtl should include("""out[1].foo <= UInt<3>("h7")""")
-
   }
 
   "vec literals can have bundle children" in {
diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 5ef062fa..0285a524 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -103,8 +103,8 @@ class DataViewSpec extends ChiselFlatSpec {
       buzz.viewAs[MyBundle] := in
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include("fizz.foo <= in.foo")
-    chirrtl should include("buzz.foo <= in.foo")
+    chirrtl should include("fizz <= in")
+    chirrtl should include("buzz <= in")
   }
 
   it should "handle viewing Vecs as their same concrete type" in {
@@ -116,8 +116,8 @@ class DataViewSpec extends ChiselFlatSpec {
       buzz.viewAs[Vec[UInt]] := in
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include("fizz[0] <= in[0]")
-    chirrtl should include("buzz[0] <= in[0]")
+    chirrtl should include("fizz <= in")
+    chirrtl should include("buzz <= in")
   }
 
   it should "handle viewing Vecs as Bundles and vice versa" in {