diff options
| author | Jack | 2017-01-30 22:33:46 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-01-31 11:30:28 -0800 |
| commit | ec5fcc2930e8ef99ea307bc1435fe323b4b79963 (patch) | |
| tree | 93bfe605c42201d53295ed3411d9106f8aee9bad /src/test/scala/chiselTests/BlackBoxImpl.scala | |
| parent | 632a7166ac1935100cb1d61add3b28d1fd4dc8f4 (diff) | |
Fix spelling of ChiselExecutionSuccess
Diffstat (limited to 'src/test/scala/chiselTests/BlackBoxImpl.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BlackBoxImpl.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala index fed04d2c..9e817486 100644 --- a/src/test/scala/chiselTests/BlackBoxImpl.scala +++ b/src/test/scala/chiselTests/BlackBoxImpl.scala @@ -68,7 +68,7 @@ class BlackBoxImplSpec extends FreeSpec with Matchers { "BlackBox can have verilator source implementation" - { "Implementations can be contained in-line" in { Driver.execute(Array("-X", "verilog"), () => new UsesBlackBoxAddViaInline) match { - case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) => + case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) => val verilogOutput = new File("./BlackBoxAdd.v") verilogOutput.exists() should be (true) verilogOutput.delete() @@ -79,7 +79,7 @@ class BlackBoxImplSpec extends FreeSpec with Matchers { } "Implementations can be contained in resource files" in { Driver.execute(Array("-X", "low"), () => new UsesBlackBoxMinusViaResource) match { - case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) => + case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) => val verilogOutput = new File("./BlackBoxTest.v") verilogOutput.exists() should be (true) verilogOutput.delete() |