From ec5fcc2930e8ef99ea307bc1435fe323b4b79963 Mon Sep 17 00:00:00 2001
From: Jack
Date: Mon, 30 Jan 2017 22:33:46 -0800
Subject: Fix spelling of ChiselExecutionSuccess

---
 src/test/scala/chiselTests/BlackBoxImpl.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests/BlackBoxImpl.scala')

diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index fed04d2c..9e817486 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -68,7 +68,7 @@ class BlackBoxImplSpec extends FreeSpec with Matchers {
   "BlackBox can have verilator source implementation" - {
     "Implementations can be contained in-line" in {
       Driver.execute(Array("-X", "verilog"), () => new UsesBlackBoxAddViaInline) match {
-        case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
           val verilogOutput = new File("./BlackBoxAdd.v")
           verilogOutput.exists() should be (true)
           verilogOutput.delete()
@@ -79,7 +79,7 @@ class BlackBoxImplSpec extends FreeSpec with Matchers {
     }
     "Implementations can be contained in resource files" in {
       Driver.execute(Array("-X", "low"), () => new UsesBlackBoxMinusViaResource) match {
-        case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
           val verilogOutput = new File("./BlackBoxTest.v")
           verilogOutput.exists() should be (true)
           verilogOutput.delete()
-- 
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