Fix spelling of ChiselExecutionSuccess

4 files changed, 7 insertions, 7 deletions

diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
index 9866c734..3f255083 100644
--- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
+++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
@@ -143,7 +143,7 @@ class AnnotatingDiamondSpec extends FreeSpec with Matchers {
       |that happens only after emit has been called on circuit""".stripMargin in {
 
       Driver.execute(Array.empty[String], () => new TopOfDiamond) match {
-        case ChiselExecutionSucccess(Some(circuit), emitted, _) =>
+        case ChiselExecutionSuccess(Some(circuit), emitted, _) =>
           val annos = circuit.annotations
           annos.length should be (10)
 
diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala
index e34444a6..7c7c0583 100644
--- a/src/test/scala/chiselTests/AnnotationNoDedup.scala
+++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala
@@ -51,7 +51,7 @@ class AnnotationNoDedup extends FreeSpec with Matchers {
   "Firrtl provides transform that reduces identical modules to a single instance" - {
     "Annotations can be added which will defeat this deduplication for specific modules instances" in {
       Driver.execute(Array("-X", "low"), () => new UsesMuchUsedModule(addAnnos = true)) match {
-        case ChiselExecutionSucccess(_, _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
+        case ChiselExecutionSuccess(_, _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
           val lowFirrtl = firrtlResult.emitted
 
           lowFirrtl should include ("module MuchUsedModule :")
@@ -64,7 +64,7 @@ class AnnotationNoDedup extends FreeSpec with Matchers {
     }
     "Turning off these nnotations dedup all the occurrences" in {
       Driver.execute(Array("-X", "low"), () => new UsesMuchUsedModule(addAnnos = false)) match {
-        case ChiselExecutionSucccess(_, _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
+        case ChiselExecutionSuccess(_, _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
           val lowFirrtl = firrtlResult.emitted
 
           lowFirrtl should include ("module MuchUsedModule :")
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index fed04d2c..9e817486 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -68,7 +68,7 @@ class BlackBoxImplSpec extends FreeSpec with Matchers {
   "BlackBox can have verilator source implementation" - {
     "Implementations can be contained in-line" in {
       Driver.execute(Array("-X", "verilog"), () => new UsesBlackBoxAddViaInline) match {
-        case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
           val verilogOutput = new File("./BlackBoxAdd.v")
           verilogOutput.exists() should be (true)
           verilogOutput.delete()
@@ -79,7 +79,7 @@ class BlackBoxImplSpec extends FreeSpec with Matchers {
     }
     "Implementations can be contained in resource files" in {
       Driver.execute(Array("-X", "low"), () => new UsesBlackBoxMinusViaResource) match {
-        case ChiselExecutionSucccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
+        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
           val verilogOutput = new File("./BlackBoxTest.v")
           verilogOutput.exists() should be (true)
           verilogOutput.delete()
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index d77dbaf1..b68b2810 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -25,8 +25,8 @@ class DriverSpec extends FreeSpec with Matchers {
     "execute returns a chisel execution result" in {
       val args = Array("--compiler", "low")
       val result = Driver.execute(Array.empty[String], () => new DummyModule)
-      result shouldBe a[ChiselExecutionSucccess]
-      val successResult = result.asInstanceOf[ChiselExecutionSucccess]
+      result shouldBe a[ChiselExecutionSuccess]
+      val successResult = result.asInstanceOf[ChiselExecutionSuccess]
       successResult.emitted should include ("circuit DummyModule")
     }
   }