Apply scalafmt

Command:
sbt scalafmtAll

67 files changed, 2118 insertions, 1716 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index aa379629..30a97df6 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -17,7 +17,8 @@ trait BackendCompilationUtilities extends LazyLogging {
   lazy val TestDirectory = FirrtlBackendCompilationUtilities.TestDirectory
   def timeStamp:            String = FirrtlBackendCompilationUtilities.timeStamp
   def loggingProcessLogger: ProcessLogger = FirrtlBackendCompilationUtilities.loggingProcessLogger
-  def copyResourceToFile(name:      String, file: File): Unit = FirrtlBackendCompilationUtilities.copyResourceToFile(name, file)
+  def copyResourceToFile(name: String, file: File): Unit =
+    FirrtlBackendCompilationUtilities.copyResourceToFile(name, file)
   def createTestDirectory(testName: String): File = FirrtlBackendCompilationUtilities.createTestDirectory(testName)
   def makeHarness(template:         String => String, post: String)(f: File): File =
     FirrtlBackendCompilationUtilities.makeHarness(template, post)(f)
@@ -98,10 +99,9 @@ trait BackendCompilationUtilities extends LazyLogging {
     import firrtl.stage.FirrtlCircuitAnnotation
 
     options.collectFirst { case a: FirrtlCircuitAnnotation => a.circuit } match {
-      case None => false
+      case None    => false
       case Some(_) => true
     }
     // *********************************************************************************************
   }
 }
-
diff --git a/src/main/scala/chisel3/aop/AspectLibrary.scala b/src/main/scala/chisel3/aop/AspectLibrary.scala
index 1a16b61f..04ac2384 100644
--- a/src/main/scala/chisel3/aop/AspectLibrary.scala
+++ b/src/main/scala/chisel3/aop/AspectLibrary.scala
@@ -8,7 +8,7 @@ import firrtl.options.{OptionsException, RegisteredLibrary, ShellOption}
 /** Enables adding aspects to a design from the commandline, e.g.
   *  sbt> runMain chisel3.stage.ChiselMain --module <module> --with-aspect <aspect>
   */
-final class AspectLibrary() extends RegisteredLibrary  {
+final class AspectLibrary() extends RegisteredLibrary {
   val name = "AspectLibrary"
 
   import scala.reflect.runtime.universe._
@@ -34,16 +34,20 @@ final class AspectLibrary() extends RegisteredLibrary  {
         throw new OptionsException(s"Unable to locate aspect '$aspectName'! (Did you misspell it?)", e)
       case e: InstantiationException =>
         throw new OptionsException(
-          s"Unable to create instance of aspect '$aspectName'! (Does this class take parameters?)", e)
+          s"Unable to create instance of aspect '$aspectName'! (Does this class take parameters?)",
+          e
+        )
     }
   }
 
-  val options = Seq(new ShellOption[String](
-    longOption = "with-aspect",
-    toAnnotationSeq = {
-      case aspectName: String => Seq(apply(aspectName))
-    },
-    helpText = "The name/class of an aspect to compile with (must be a class/object without arguments!)",
-    helpValueName = Some("<package>.<aspect>")
-  ))
+  val options = Seq(
+    new ShellOption[String](
+      longOption = "with-aspect",
+      toAnnotationSeq = {
+        case aspectName: String => Seq(apply(aspectName))
+      },
+      helpText = "The name/class of an aspect to compile with (must be a class/object without arguments!)",
+      helpValueName = Some("<package>.<aspect>")
+    )
+  )
 }
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index 6bd13445..3a2a8931 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -47,17 +47,18 @@ object Select {
     */
   def instancesIn(parent: Hierarchy[BaseModule]): Seq[Instance[BaseModule]] = {
     check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated{}
+    implicit val mg = new chisel3.internal.MacroGenerated {}
     parent.proto._component.get match {
-      case d: DefModule => d.commands.collect {
-        case d: DefInstance =>
-          d.id match {
-            case p: chisel3.internal.BaseModule.IsClone[_] =>
-              parent._lookup { x => new Instance(Clone(p)).asInstanceOf[Instance[BaseModule]] }
-            case other: BaseModule =>
-              parent._lookup { x => other }
-          }
-      }
+      case d: DefModule =>
+        d.commands.collect {
+          case d: DefInstance =>
+            d.id match {
+              case p: chisel3.internal.BaseModule.IsClone[_] =>
+                parent._lookup { x => new Instance(Clone(p)).asInstanceOf[Instance[BaseModule]] }
+              case other: BaseModule =>
+                parent._lookup { x => other }
+            }
+        }
       case other => Nil
     }
   }
@@ -66,25 +67,26 @@ object Select {
     *
     * @note IMPORTANT: this function requires summoning a TypeTag[T], which will fail if T is an inner class.
     * @note IMPORTANT: this function ignores type parameters. E.g. instancesOf[List[Int]] would return List[String].
-    * 
+    *
     * @param parent hierarchy which instantiates the returned Definitions
     */
-  def instancesOf[T <: BaseModule : TypeTag](parent: Hierarchy[BaseModule]): Seq[Instance[T]] = {
+  def instancesOf[T <: BaseModule: TypeTag](parent: Hierarchy[BaseModule]): Seq[Instance[T]] = {
     check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated{}
+    implicit val mg = new chisel3.internal.MacroGenerated {}
     parent.proto._component.get match {
-      case d: DefModule => d.commands.flatMap {
-        case d: DefInstance =>
-          d.id match {
-            case p: chisel3.internal.BaseModule.IsClone[_] =>
-              val i = parent._lookup { x => new Instance(Clone(p)).asInstanceOf[Instance[BaseModule]] }
-              if(i.isA[T]) Some(i.asInstanceOf[Instance[T]]) else None
-            case other: BaseModule =>
-              val i = parent._lookup { x => other }
-              if(i.isA[T]) Some(i.asInstanceOf[Instance[T]]) else None
-          }
-        case other => None
-      }
+      case d: DefModule =>
+        d.commands.flatMap {
+          case d: DefInstance =>
+            d.id match {
+              case p: chisel3.internal.BaseModule.IsClone[_] =>
+                val i = parent._lookup { x => new Instance(Clone(p)).asInstanceOf[Instance[BaseModule]] }
+                if (i.isA[T]) Some(i.asInstanceOf[Instance[T]]) else None
+              case other: BaseModule =>
+                val i = parent._lookup { x => other }
+                if (i.isA[T]) Some(i.asInstanceOf[Instance[T]]) else None
+            }
+          case other => None
+        }
       case other => Nil
     }
   }
@@ -96,39 +98,40 @@ object Select {
     *
     * @param root top of the hierarchy to search for instances/modules of given type
     */
-  def allInstancesOf[T <: BaseModule : TypeTag](root: Hierarchy[BaseModule]): Seq[Instance[T]] = {
-    val soFar = if(root.isA[T]) Seq(root.toInstance.asInstanceOf[Instance[T]]) else Nil
+  def allInstancesOf[T <: BaseModule: TypeTag](root: Hierarchy[BaseModule]): Seq[Instance[T]] = {
+    val soFar = if (root.isA[T]) Seq(root.toInstance.asInstanceOf[Instance[T]]) else Nil
     val allLocalInstances = instancesIn(root)
     soFar ++ (allLocalInstances.flatMap(allInstancesOf[T]))
   }
 
   /** Selects the Definitions of all instances/modules directly instantiated within given module
-    * 
+    *
     * @param parent
     */
   def definitionsIn(parent: Hierarchy[BaseModule]): Seq[Definition[BaseModule]] = {
     type DefType = Definition[BaseModule]
-    implicit val mg = new chisel3.internal.MacroGenerated{}
+    implicit val mg = new chisel3.internal.MacroGenerated {}
     check(parent)
     val defs = parent.proto._component.get match {
-      case d: DefModule => d.commands.collect {
-        case i: DefInstance =>
-          i.id match {
-            case p: chisel3.internal.BaseModule.IsClone[_] =>
-              parent._lookup { x => new Definition(Proto(p.getProto)).asInstanceOf[Definition[BaseModule]] }
-            case other: BaseModule =>
-              parent._lookup { x => other.toDefinition }
-          }
-      }
+      case d: DefModule =>
+        d.commands.collect {
+          case i: DefInstance =>
+            i.id match {
+              case p: chisel3.internal.BaseModule.IsClone[_] =>
+                parent._lookup { x => new Definition(Proto(p.getProto)).asInstanceOf[Definition[BaseModule]] }
+              case other: BaseModule =>
+                parent._lookup { x => other.toDefinition }
+            }
+        }
       case other => Nil
     }
-    val (_, defList) = defs.foldLeft((Set.empty[DefType], List.empty[DefType])) { case ((set, list), definition: Definition[BaseModule]) =>
-      if(set.contains(definition)) (set, list) else (set + definition, definition +: list)
+    val (_, defList) = defs.foldLeft((Set.empty[DefType], List.empty[DefType])) {
+      case ((set, list), definition: Definition[BaseModule]) =>
+        if (set.contains(definition)) (set, list) else (set + definition, definition +: list)
     }
     defList.reverse
   }
 
-
   /** Selects all Definitions of instances/modules directly instantiated within given module, of provided type
     *
     * @note IMPORTANT: this function requires summoning a TypeTag[T], which will fail if T is an inner class.
@@ -136,26 +139,28 @@ object Select {
     *
     * @param parent hierarchy which instantiates the returned Definitions
     */
-  def definitionsOf[T <: BaseModule : TypeTag](parent: Hierarchy[BaseModule]): Seq[Definition[T]] = {
+  def definitionsOf[T <: BaseModule: TypeTag](parent: Hierarchy[BaseModule]): Seq[Definition[T]] = {
     check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated{}
+    implicit val mg = new chisel3.internal.MacroGenerated {}
     type DefType = Definition[T]
     val defs = parent.proto._component.get match {
-      case d: DefModule => d.commands.flatMap {
-        case d: DefInstance =>
-          d.id match {
-            case p: chisel3.internal.BaseModule.IsClone[_] =>
-              val d = parent._lookup { x => new Definition(Clone(p)).asInstanceOf[Definition[BaseModule]] }
-              if(d.isA[T]) Some(d.asInstanceOf[Definition[T]]) else None
-            case other: BaseModule =>
-              val d = parent._lookup { x => other.toDefinition }
-              if(d.isA[T]) Some(d.asInstanceOf[Definition[T]]) else None
-          }
-        case other => None
-      }
+      case d: DefModule =>
+        d.commands.flatMap {
+          case d: DefInstance =>
+            d.id match {
+              case p: chisel3.internal.BaseModule.IsClone[_] =>
+                val d = parent._lookup { x => new Definition(Clone(p)).asInstanceOf[Definition[BaseModule]] }
+                if (d.isA[T]) Some(d.asInstanceOf[Definition[T]]) else None
+              case other: BaseModule =>
+                val d = parent._lookup { x => other.toDefinition }
+                if (d.isA[T]) Some(d.asInstanceOf[Definition[T]]) else None
+            }
+          case other => None
+        }
     }
-    val (_, defList) = defs.foldLeft((Set.empty[DefType], List.empty[DefType])) { case ((set, list), definition: Definition[T]) =>
-      if(set.contains(definition)) (set, list) else (set + definition, definition +: list)
+    val (_, defList) = defs.foldLeft((Set.empty[DefType], List.empty[DefType])) {
+      case ((set, list), definition: Definition[T]) =>
+        if (set.contains(definition)) (set, list) else (set + definition, definition +: list)
     }
     defList.reverse
   }
@@ -168,14 +173,14 @@ object Select {
     *
     * @param root top of the hierarchy to search for definitions of given type
     */
-  def allDefinitionsOf[T <: BaseModule : TypeTag](root: Hierarchy[BaseModule]): Seq[Definition[T]] = {
+  def allDefinitionsOf[T <: BaseModule: TypeTag](root: Hierarchy[BaseModule]): Seq[Definition[T]] = {
     type DefType = Definition[T]
     val allDefSet = mutable.HashSet[Definition[BaseModule]]()
     val defSet = mutable.HashSet[DefType]()
     val defList = mutable.ArrayBuffer[DefType]()
     def rec(hier: Definition[BaseModule]): Unit = {
-      if(hier.isA[T] && !defSet.contains(hier.asInstanceOf[DefType])) {
-        defSet  += hier.asInstanceOf[DefType]
+      if (hier.isA[T] && !defSet.contains(hier.asInstanceOf[DefType])) {
+        defSet += hier.asInstanceOf[DefType]
         defList += hier.asInstanceOf[DefType]
       }
       allDefSet += hier
@@ -188,7 +193,6 @@ object Select {
     defList.toList
   }
 
-
   /** Collects all components selected by collector within module and all children modules it instantiates
     *   directly or indirectly
     * Accepts a collector function, rather than a collector partial function (see [[collectDeep]])
@@ -203,8 +207,8 @@ object Select {
   def getDeep[T](module: BaseModule)(collector: BaseModule => Seq[T]): Seq[T] = {
     check(module)
     val myItems = collector(module)
-    val deepChildrenItems = instances(module).flatMap {
-      i => getDeep(i)(collector)
+    val deepChildrenItems = instances(module).flatMap { i =>
+      getDeep(i)(collector)
     }
     myItems ++ deepChildrenItems
   }
@@ -223,8 +227,8 @@ object Select {
   def collectDeep[T](module: BaseModule)(collector: PartialFunction[BaseModule, T]): Iterable[T] = {
     check(module)
     val myItems = collector.lift(module)
-    val deepChildrenItems = instances(module).flatMap {
-      i => collectDeep(i)(collector)
+    val deepChildrenItems = instances(module).flatMap { i =>
+      collectDeep(i)(collector)
     }
     myItems ++ deepChildrenItems
   }
@@ -238,14 +242,19 @@ object Select {
   def instances(module: BaseModule): Seq[BaseModule] = {
     check(module)
     module._component.get match {
-      case d: DefModule => d.commands.flatMap {
-        case i: DefInstance => i.id match {
-          case m: ModuleClone[_] if !m._madeFromDefinition => None
-          case _: PseudoModule => throw new Exception("instances, collectDeep, and getDeep are currently incompatible with Definition/Instance!")
-          case other          => Some(other)
+      case d: DefModule =>
+        d.commands.flatMap {
+          case i: DefInstance =>
+            i.id match {
+              case m: ModuleClone[_] if !m._madeFromDefinition => None
+              case _: PseudoModule =>
+                throw new Exception(
+                  "instances, collectDeep, and getDeep are currently incompatible with Definition/Instance!"
+                )
+              case other => Some(other)
+            }
+          case _ => None
         }
-        case _ => None
-      }
       case other => Nil
     }
   }
@@ -256,7 +265,7 @@ object Select {
   def registers(module: BaseModule): Seq[Data] = {
     check(module)
     module._component.get.asInstanceOf[DefModule].commands.collect {
-      case r: DefReg => r.id
+      case r: DefReg     => r.id
       case r: DefRegInit => r.id
     }
   }
@@ -274,7 +283,7 @@ object Select {
     */
   def ios[T <: BaseModule](parent: Hierarchy[T]): Seq[Data] = {
     check(parent)
-    implicit val mg = new chisel3.internal.MacroGenerated{}
+    implicit val mg = new chisel3.internal.MacroGenerated {}
     parent._lookup { x => ios(parent.proto) }
   }
 
@@ -366,9 +375,14 @@ object Select {
     */
   def attachedTo(module: BaseModule)(signal: Data): Set[Data] = {
     check(module)
-    module._component.get.asInstanceOf[DefModule].commands.collect {
-      case Attach(_, seq) if seq.contains(signal) => seq
-    }.flatMap { seq => seq.map(_.id.asInstanceOf[Data]) }.toSet
+    module._component.get
+      .asInstanceOf[DefModule]
+      .commands
+      .collect {
+        case Attach(_, seq) if seq.contains(signal) => seq
+      }
+      .flatMap { seq => seq.map(_.id.asInstanceOf[Data]) }
+      .toSet
   }
 
   /** Selects all connections to a signal or its parent signal(s) (if the signal is an element of an aggregate signal)
@@ -382,31 +396,42 @@ object Select {
     check(module)
     val sensitivitySignals = getIntermediateAndLeafs(signal).toSet
     val predicatedConnects = mutable.ArrayBuffer[PredicatedConnect]()
-    val isPort = module._component.get.asInstanceOf[DefModule].ports.flatMap{ p => getIntermediateAndLeafs(p.id) }.contains(signal)
+    val isPort = module._component.get
+      .asInstanceOf[DefModule]
+      .ports
+      .flatMap { p => getIntermediateAndLeafs(p.id) }
+      .contains(signal)
     var prePredicates: Seq[Predicate] = Nil
     var seenDef = isPort
-    searchWhens(module, (cmd: Command, preds) => {
-      cmd match {
-        case cmd: DefinitionIR if cmd.id.isInstanceOf[Data] =>
-          val x = getIntermediateAndLeafs(cmd.id.asInstanceOf[Data])
-          if(x.contains(signal)) prePredicates = preds
-        case Connect(_, loc@Node(d: Data), exp) =>
-          val effected = getEffected(loc).toSet
-          if(sensitivitySignals.intersect(effected).nonEmpty) {
-            val expData = getData(exp)
-            prePredicates.reverse.zip(preds.reverse).foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
-            predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = false)
-          }
-        case BulkConnect(_, loc@Node(d: Data), exp) =>
-          val effected = getEffected(loc).toSet
-          if(sensitivitySignals.intersect(effected).nonEmpty) {
-            val expData = getData(exp)
-            prePredicates.reverse.zip(preds.reverse).foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
-            predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = true)
-          }
-        case other =>
+    searchWhens(
+      module,
+      (cmd: Command, preds) => {
+        cmd match {
+          case cmd: DefinitionIR if cmd.id.isInstanceOf[Data] =>
+            val x = getIntermediateAndLeafs(cmd.id.asInstanceOf[Data])
+            if (x.contains(signal)) prePredicates = preds
+          case Connect(_, loc @ Node(d: Data), exp) =>
+            val effected = getEffected(loc).toSet
+            if (sensitivitySignals.intersect(effected).nonEmpty) {
+              val expData = getData(exp)
+              prePredicates.reverse
+                .zip(preds.reverse)
+                .foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
+              predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = false)
+            }
+          case BulkConnect(_, loc @ Node(d: Data), exp) =>
+            val effected = getEffected(loc).toSet
+            if (sensitivitySignals.intersect(effected).nonEmpty) {
+              val expData = getData(exp)
+              prePredicates.reverse
+                .zip(preds.reverse)
+                .foreach(x => assert(x._1 == x._2, s"Prepredicates $x must match for signal $signal"))
+              predicatedConnects += PredicatedConnect(preds.dropRight(prePredicates.size), d, expData, isBulk = true)
+            }
+          case other =>
+        }
       }
-    })
+    )
     predicatedConnects.toSeq
   }
 
@@ -414,14 +439,18 @@ object Select {
     *
     * @param module
     */
-  def stops(module: BaseModule): Seq[Stop]  = {
+  def stops(module: BaseModule): Seq[Stop] = {
     val stops = mutable.ArrayBuffer[Stop]()
-    searchWhens(module, (cmd: Command, preds: Seq[Predicate]) => {
-      cmd match {
-        case chisel3.internal.firrtl.Stop(_, _, clock, ret) => stops += Stop(preds, ret, getId(clock).asInstanceOf[Clock])
-        case other =>
+    searchWhens(
+      module,
+      (cmd: Command, preds: Seq[Predicate]) => {
+        cmd match {
+          case chisel3.internal.firrtl.Stop(_, _, clock, ret) =>
+            stops += Stop(preds, ret, getId(clock).asInstanceOf[Clock])
+          case other =>
+        }
       }
-    })
+    )
     stops.toSeq
   }
 
@@ -431,12 +460,16 @@ object Select {
     */
   def printfs(module: BaseModule): Seq[Printf] = {
     val printfs = mutable.ArrayBuffer[Printf]()
-    searchWhens(module, (cmd: Command, preds: Seq[Predicate]) => {
-      cmd match {
-        case chisel3.internal.firrtl.Printf(id, _, clock, pable) => printfs += Printf(id, preds, pable, getId(clock).asInstanceOf[Clock])
-        case other =>
+    searchWhens(
+      module,
+      (cmd: Command, preds: Seq[Predicate]) => {
+        cmd match {
+          case chisel3.internal.firrtl.Printf(id, _, clock, pable) =>
+            printfs += Printf(id, preds, pable, getId(clock).asInstanceOf[Clock])
+          case other =>
+        }
       }
-    })
+    )
     printfs.toSeq
   }
 
@@ -450,15 +483,15 @@ object Select {
   // Given a loc, return all subcomponents of id that could be assigned to in connect
   private def getEffected(a: Arg): Seq[Data] = a match {
     case Node(id: Data) => getIntermediateAndLeafs(id)
-    case Slot(imm, name) => Seq(imm.id.asInstanceOf[Record].elements(name))
+    case Slot(imm, name)   => Seq(imm.id.asInstanceOf[Record].elements(name))
     case Index(imm, value) => getEffected(imm)
   }
 
   // Given an arg, return the corresponding id. Don't use on a loc of a connect.
   private def getId(a: Arg): HasId = a match {
     case Node(id) => id
-    case l: ULit => l.num.U(l.w)
-    case l: SLit => l.num.S(l.w)
+    case l: ULit  => l.num.U(l.w)
+    case l: SLit  => l.num.S(l.w)
     case l: FPLit => FixedPoint(l.num, l.w, l.binaryPoint)
     case other =>
       sys.error(s"Something went horribly wrong! I was expecting ${other} to be a lit or a node!")
@@ -478,9 +511,10 @@ object Select {
         str.splitAt(str.indexOf('>'))._2.drop(1)
     }
   } catch {
-    case e: ChiselException => i.getOptionRef.get match {
-      case l: LitArg => l.num.intValue.toString
-    }
+    case e: ChiselException =>
+      i.getOptionRef.get match {
+        case l: LitArg => l.num.intValue.toString
+      }
   }
 
   // Collects when predicates as it searches through a module, then applying processCommand to non-when related commands
@@ -489,21 +523,22 @@ object Select {
     module._component.get.asInstanceOf[DefModule].commands.foldLeft((Seq.empty[Predicate], Option.empty[Predicate])) {
       (blah, cmd) =>
         (blah, cmd) match {
-          case ((preds, o), cmd) => cmd match {
-            case WhenBegin(_, Node(pred: Bool)) => (When(pred) +: preds, None)
-            case WhenBegin(_, l: LitArg) if l.num == BigInt(1) => (When(true.B) +: preds, None)
-            case WhenBegin(_, l: LitArg) if l.num == BigInt(0) => (When(false.B) +: preds, None)
-            case other: WhenBegin =>
-              sys.error(s"Something went horribly wrong! I was expecting ${other.pred} to be a lit or a bool!")
-            case _: WhenEnd => (preds.tail, Some(preds.head))
-            case AltBegin(_) if o.isDefined => (o.get.not +: preds, o)
-            case _: AltBegin =>
-              sys.error(s"Something went horribly wrong! I was expecting ${o} to be nonEmpty!")
-            case OtherwiseEnd(_, _) => (preds.tail, None)
-            case other =>
-              processCommand(cmd, preds)
-              (preds, o)
-          }
+          case ((preds, o), cmd) =>
+            cmd match {
+              case WhenBegin(_, Node(pred: Bool)) => (When(pred) +: preds, None)
+              case WhenBegin(_, l: LitArg) if l.num == BigInt(1) => (When(true.B) +: preds, None)
+              case WhenBegin(_, l: LitArg) if l.num == BigInt(0) => (When(false.B) +: preds, None)
+              case other: WhenBegin =>
+                sys.error(s"Something went horribly wrong! I was expecting ${other.pred} to be a lit or a bool!")
+              case _: WhenEnd => (preds.tail, Some(preds.head))
+              case AltBegin(_) if o.isDefined => (o.get.not +: preds, o)
+              case _: AltBegin =>
+                sys.error(s"Something went horribly wrong! I was expecting ${o} to be nonEmpty!")
+              case OtherwiseEnd(_, _) => (preds.tail, None)
+              case other =>
+                processCommand(cmd, preds)
+                (preds, o)
+            }
         }
     }
   }
@@ -524,7 +559,7 @@ object Select {
     * @param bool the when predicate
     */
   case class When(bool: Bool) extends Predicate {
-    def not: WhenNot = WhenNot(bool)
+    def not:       WhenNot = WhenNot(bool)
     def serialize: String = s"${getName(bool)}"
   }
 
@@ -533,7 +568,7 @@ object Select {
     * @param bool the when predicate corresponding to this otherwise predicate
     */
   case class WhenNot(bool: Bool) extends Predicate {
-    def not: When = When(bool)
+    def not:       When = When(bool)
     def serialize: String = s"!${getName(bool)}"
   }
 
@@ -549,7 +584,7 @@ object Select {
   case class PredicatedConnect(preds: Seq[Predicate], loc: Data, exp: Data, isBulk: Boolean) extends Serializeable {
     def serialize: String = {
       val moduleTarget = loc.toTarget.moduleTarget.serialize
-      s"$moduleTarget: when(${preds.map(_.serialize).mkString(" & ")}): ${getName(loc)} ${if(isBulk) "<>" else ":="} ${getName(exp)}"
+      s"$moduleTarget: when(${preds.map(_.serialize).mkString(" & ")}): ${getName(loc)} ${if (isBulk) "<>" else ":="} ${getName(exp)}"
     }
   }
 
diff --git a/src/main/scala/chisel3/aop/injecting/InjectStatement.scala b/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
index 92e24ba1..dbe1fd7b 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
@@ -15,7 +15,12 @@ import firrtl.annotations.{Annotation, ModuleTarget, NoTargetAnnotation, SingleT
   * @param modules Additional modules that may be instantiated by s
   * @param annotations Additional annotations that should be passed down compiler
   */
-case class InjectStatement(module: ModuleTarget, s: firrtl.ir.Statement, modules: Seq[firrtl.ir.DefModule], annotations: Seq[Annotation]) extends SingleTargetAnnotation[ModuleTarget] {
+case class InjectStatement(
+  module:      ModuleTarget,
+  s:           firrtl.ir.Statement,
+  modules:     Seq[firrtl.ir.DefModule],
+  annotations: Seq[Annotation])
+    extends SingleTargetAnnotation[ModuleTarget] {
   val target: ModuleTarget = module
   override def duplicate(n: ModuleTarget): Annotation = this.copy(module = n)
 }
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
index ed59d4fb..abe208cf 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
@@ -2,7 +2,7 @@
 
 package chisel3.aop.injecting
 
-import chisel3.{Module, ModuleAspect, RawModule, withClockAndReset}
+import chisel3.{withClockAndReset, Module, ModuleAspect, RawModule}
 import chisel3.aop._
 import chisel3.internal.{Builder, DynamicContext}
 import chisel3.internal.firrtl.DefModule
@@ -22,12 +22,12 @@ import scala.collection.mutable
   * @tparam M Type of root module (join point)
   */
 case class InjectingAspect[T <: RawModule, M <: RawModule](
-    selectRoots: T => Iterable[M],
-    injection: M => Unit
-) extends InjectorAspect[T, M](
-    selectRoots,
-    injection
-)
+  selectRoots: T => Iterable[M],
+  injection:   M => Unit)
+    extends InjectorAspect[T, M](
+      selectRoots,
+      injection
+    )
 
 /** Extend to inject Chisel code into a module of type M
   *
@@ -38,11 +38,12 @@ case class InjectingAspect[T <: RawModule, M <: RawModule](
   * @tparam M Type of root module (join point)
   */
 abstract class InjectorAspect[T <: RawModule, M <: RawModule](
-    selectRoots: T => Iterable[M],
-    injection: M => Unit
-) extends Aspect[T] {
+  selectRoots: T => Iterable[M],
+  injection:   M => Unit)
+    extends Aspect[T] {
   final def toAnnotation(top: T): AnnotationSeq = {
-    val moduleNames = Select.allDefinitionsOf[chisel3.experimental.BaseModule](top.toDefinition).map{i => i.toTarget.module }.toSeq
+    val moduleNames =
+      Select.allDefinitionsOf[chisel3.experimental.BaseModule](top.toDefinition).map { i => i.toTarget.module }.toSeq
     toAnnotation(selectRoots(top), top.name, moduleNames)
   }
 
@@ -62,22 +63,26 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule](
         dynamicContext.globalNamespace.name(n)
       }
 
-      val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) {
-        module match {
-          case x: Module => withClockAndReset(x.clock, x.reset) { injection(module) }
-          case x: RawModule => injection(module)
-        }
-      }), dynamicContext)
+      val (chiselIR, _) = Builder.build(
+        Module(new ModuleAspect(module) {
+          module match {
+            case x: Module    => withClockAndReset(x.clock, x.reset) { injection(module) }
+            case x: RawModule => injection(module)
+          }
+        }),
+        dynamicContext
+      )
 
       val comps = chiselIR.components.map {
         case x: DefModule if x.name == module.name => x.copy(id = module)
         case other => other
       }
 
-      val annotations = chiselIR.annotations.map(_.toFirrtl).filterNot{ a => a.isInstanceOf[DesignAnnotation[_]] }
+      val annotations = chiselIR.annotations.map(_.toFirrtl).filterNot { a => a.isInstanceOf[DesignAnnotation[_]] }
 
       /** Statements to be injected via aspect. */
       val stmts = mutable.ArrayBuffer[ir.Statement]()
+
       /** Modules to be injected via aspect. */
       val modules = Aspect.getFirrtl(chiselIR.copy(components = comps)).modules.flatMap {
         // for "container" modules, inject their statements
@@ -93,4 +98,3 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule](
     }.toSeq
   }
 }
-
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala b/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
index cc5601b1..8a0b6ecb 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
@@ -2,7 +2,7 @@
 
 package chisel3.aop.injecting
 
-import firrtl.{ChirrtlForm, CircuitForm, CircuitState, Transform, ir}
+import firrtl.{ir, ChirrtlForm, CircuitForm, CircuitState, Transform}
 
 import scala.collection.mutable
 
@@ -11,7 +11,7 @@ import scala.collection.mutable
   * Implemented with Chisel Aspects and the [[chisel3.aop.injecting]] library
   */
 class InjectingTransform extends Transform {
-  override def inputForm: CircuitForm = ChirrtlForm
+  override def inputForm:  CircuitForm = ChirrtlForm
   override def outputForm: CircuitForm = ChirrtlForm
 
   override def execute(state: CircuitState): CircuitState = {
diff --git a/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala b/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala
index a9752426..1340f253 100644
--- a/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala
+++ b/src/main/scala/chisel3/aop/inspecting/InspectingAspect.scala
@@ -13,7 +13,6 @@ import firrtl.AnnotationSeq
   */
 case class InspectingAspect[T <: RawModule](inspect: T => Unit) extends InspectorAspect[T](inspect)
 
-
 /** Extend to make custom inspections of an elaborated design and printing out results
   *
   * @param inspect Given top-level design, print things and return nothing
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index ccb4ec1f..f3754e00 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -3,10 +3,10 @@
 /** The Chisel compatibility package allows legacy users to continue using the `Chisel` (capital C) package name
   *  while moving to the more standard package naming convention `chisel3` (lowercase c).
   */
-import chisel3._    // required for implicit conversions.
+import chisel3._ // required for implicit conversions.
 import chisel3.experimental.chiselName
 import chisel3.util.random.FibonacciLFSR
-import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage, phases}
+import chisel3.stage.{phases, ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage}
 
 package object Chisel {
   import chisel3.internal.firrtl.Width
@@ -23,23 +23,26 @@ package object Chisel {
   case object OUTPUT extends Direction
   case object NODIR extends Direction
 
-  val Input   = chisel3.Input
-  val Output  = chisel3.Output
+  val Input = chisel3.Input
+  val Output = chisel3.Output
 
   object Flipped {
-    def apply[T<:Data](target: T): T = chisel3.Flipped[T](target)
+    def apply[T <: Data](target: T): T = chisel3.Flipped[T](target)
   }
 
-  implicit class AddDirectionToData[T<:Data](target: T) {
-    def asInput: T = Input(target)
+  implicit class AddDirectionToData[T <: Data](target: T) {
+    def asInput:  T = Input(target)
     def asOutput: T = Output(target)
-    def flip: T = Flipped(target)
+    def flip:     T = Flipped(target)
 
-    @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+    @deprecated(
+      "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead",
+      "Chisel 3.5"
+    )
     def flip(dummy: Int*): T = flip
   }
 
-  implicit class AddDirMethodToData[T<:Data](target: T) {
+  implicit class AddDirMethodToData[T <: Data](target: T) {
     import chisel3.ActualDirection
     import chisel3.experimental.DataMirror
     import chisel3.internal.requireIsHardware
@@ -47,11 +50,12 @@ package object Chisel {
     def dir: Direction = {
       requireIsHardware(target) // This has the side effect of calling _autoWrapPorts
       target match {
-        case e: Element => DataMirror.directionOf(e) match {
-          case ActualDirection.Output => OUTPUT
-          case ActualDirection.Input => INPUT
-          case _ => NODIR
-        }
+        case e: Element =>
+          DataMirror.directionOf(e) match {
+            case ActualDirection.Output => OUTPUT
+            case ActualDirection.Input  => INPUT
+            case _                      => NODIR
+          }
         case _ => NODIR
       }
     }
@@ -81,9 +85,9 @@ package object Chisel {
     def apply(dir: Direction): Clock = {
       val result = apply()
       dir match {
-        case INPUT => Input(result)
+        case INPUT  => Input(result)
         case OUTPUT => Output(result)
-        case _ => result
+        case _      => result
       }
     }
   }
@@ -130,20 +134,33 @@ package object Chisel {
       apply(Seq.fill(n)(gen))
 
     def apply[T <: Data](elts: Seq[T]): Vec[T] = macro VecTransform.apply_elts
+
     /** @group SourceInfoTransformMacro */
     def do_apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
       chisel3.VecInit(elts)
 
     def apply[T <: Data](elt0: T, elts: T*): Vec[T] = macro VecTransform.apply_elt0
+
     /** @group SourceInfoTransformMacro */
-    def do_apply[T <: Data](elt0: T, elts: T*)
-        (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
+    def do_apply[T <: Data](
+      elt0: T,
+      elts: T*
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): Vec[T] =
       chisel3.VecInit(elt0 +: elts.toSeq)
 
     def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate
+
     /** @group SourceInfoTransformMacro */
-    def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)
-        (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
+    def do_tabulate[T <: Data](
+      n:   Int
+    )(gen: (Int) => T
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): Vec[T] =
       chisel3.VecInit.tabulate(n)(gen)
   }
   type Vec[T <: Data] = chisel3.Vec[T]
@@ -157,8 +174,10 @@ package object Chisel {
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
     */
   trait UIntFactory extends chisel3.UIntFactory {
+
     /** Create a UInt literal with inferred width. */
     def apply(n: String): UInt = n.asUInt
+
     /** Create a UInt literal with fixed width. */
     def apply(n: String, width: Int): UInt = n.asUInt(width.W)
 
@@ -171,19 +190,21 @@ package object Chisel {
     /** Create a UInt with a specified width - compatibility with Chisel2. */
     // NOTE: This resolves UInt(width = 32)
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(width.W)
+
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
     def apply(value: BigInt): UInt = value.asUInt
 
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
     def apply(dir: Direction, width: Int): UInt = apply(dir, width.W)
+
     /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
     def apply(dir: Direction): UInt = apply(dir, Width())
     def apply(dir: Direction, width: Width): UInt = {
       val result = apply(width)
       dir match {
-        case INPUT => Input(result)
+        case INPUT  => Input(result)
         case OUTPUT => Output(result)
-        case NODIR => result
+        case NODIR  => result
       }
     }
 
@@ -197,13 +218,16 @@ package object Chisel {
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
     */
   trait SIntFactory extends chisel3.SIntFactory {
+
     /** Create a SInt type or port with fixed width. */
     def width(width: Int): SInt = apply(width.W)
+
     /** Create an SInt type with specified width. */
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
     def apply(value: BigInt): SInt = value.asSInt
+
     /** Create an SInt literal with fixed width. */
     def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
@@ -215,16 +239,18 @@ package object Chisel {
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
     def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
+
     /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
     def apply(dir: Direction, width: Int): SInt = apply(dir, width.W)
+
     /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
     def apply(dir: Direction): SInt = apply(dir, Width())
     def apply(dir: Direction, width: Width): SInt = {
       val result = apply(width)
       dir match {
-        case INPUT => Input(result)
+        case INPUT  => Input(result)
         case OUTPUT => Output(result)
-        case NODIR => result
+        case NODIR  => result
       }
     }
   }
@@ -232,6 +258,7 @@ package object Chisel {
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
     */
   trait BoolFactory extends chisel3.BoolFactory {
+
     /** Creates Bool literal.
       */
     def apply(x: Boolean): Bool = x.B
@@ -240,9 +267,9 @@ package object Chisel {
     def apply(dir: Direction): Bool = {
       val result = apply()
       dir match {
-        case INPUT => Input(result)
+        case INPUT  => Input(result)
         case OUTPUT => Output(result)
-        case NODIR => result
+        case NODIR  => result
       }
     }
   }
@@ -286,12 +313,22 @@ package object Chisel {
   implicit class SeqMemCompatibility(a: SeqMem.type) {
     import chisel3.internal.sourceinfo.SourceInfo
 
-    def apply[T <: Data](t: T, size: BigInt)
-        (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] =
+    def apply[T <: Data](
+      t:    T,
+      size: BigInt
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): SyncReadMem[T] =
       a.do_apply(size, t)
 
-    def apply[T <: Data](t: T, size: Int)
-        (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SyncReadMem[T] =
+    def apply[T <: Data](
+      t:    T,
+      size: Int
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): SyncReadMem[T] =
       a.do_apply(size, t)
   }
 
@@ -329,8 +366,14 @@ package object Chisel {
       * is a valid value. In those cases, you can either use the outType only Reg
       * constructor or pass in `null.asInstanceOf[T]`.
       */
-    def apply[T <: Data](t: T = null, next: T = null, init: T = null)
-        (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+    def apply[T <: Data](
+      t:    T = null,
+      next: T = null,
+      init: T = null
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): T = {
       if (t ne null) {
         val reg = if (init ne null) {
           RegInit(t, init)
@@ -386,19 +429,19 @@ package object Chisel {
     def apply[T <: Module](args: Array[String], gen: () => T): Unit =
       Predef.assert(false, "No more chiselMain in Chisel3")
 
-    def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
+    def run[T <: Module](args: Array[String], gen: () => T): Unit = {
       val circuit = ChiselStage.elaborate(gen())
       parseArgs(args)
       val output_file = new File(target_dir.getOrElse(new File(".").getCanonicalPath) + "/" + circuit.name + ".fir")
 
-      (new phases.Emitter).transform(Seq(ChiselCircuitAnnotation(circuit),
-                                         ChiselOutputFileAnnotation(output_file.toString)))
+      (new phases.Emitter)
+        .transform(Seq(ChiselCircuitAnnotation(circuit), ChiselOutputFileAnnotation(output_file.toString)))
     }
   }
 
   @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
   object debug {
-    def apply (arg: Data): Data = arg
+    def apply(arg: Data): Data = arg
   }
 
   // Deprecated as of Chsiel3
@@ -423,7 +466,7 @@ package object Chisel {
   object log2Up {
     def apply(in: BigInt): Int = {
       require(in >= 0)
-      1 max (in-1).bitLength
+      1.max((in - 1).bitLength)
     }
     def apply(in: Int): Int = apply(BigInt(in))
   }
@@ -431,7 +474,7 @@ package object Chisel {
   /** Compute the log2 rounded down with min value of 1 */
   object log2Down {
     def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1)
-    def apply(in: Int): Int = apply(BigInt(in))
+    def apply(in: Int):    Int = apply(BigInt(in))
   }
 
   val BitPat = chisel3.util.BitPat
@@ -472,8 +515,13 @@ package object Chisel {
   val Queue = chisel3.util.Queue
   type Queue[T <: Data] = QueueCompatibility[T]
 
-  sealed class QueueCompatibility[T <: Data](gen: T, entries: Int, pipe: Boolean = false, flow: Boolean = false)
-                                 (implicit compileOptions: chisel3.CompileOptions)
+  sealed class QueueCompatibility[T <: Data](
+    gen:     T,
+    entries: Int,
+    pipe:    Boolean = false,
+    flow:    Boolean = false
+  )(
+    implicit compileOptions: chisel3.CompileOptions)
       extends chisel3.util.Queue[T](gen, entries, pipe, flow)(compileOptions) {
 
     def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, override_reset: Option[Bool]) = {
@@ -489,6 +537,7 @@ package object Chisel {
   }
 
   object Enum extends chisel3.util.Enum {
+
     /** Returns n unique values of the specified type. Can be used with unpacking to define enums.
       *
       * nodeType must be of UInt type (note that Bits() creates a UInt) with unspecified width.
@@ -522,10 +571,10 @@ package object Chisel {
       * Deprecation is only to nag users to do something safer.
       */
     @deprecated("Use list-based Enum", "not soon enough")
-    def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = {
+    def apply[T <: Bits](nodeType: T, l: Symbol*): Map[Symbol, T] = {
       require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
       require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
-      (l zip createValues(l.length)).toMap.asInstanceOf[Map[Symbol, T]]
+      (l.zip(createValues(l.length))).toMap.asInstanceOf[Map[Symbol, T]]
     }
 
     /** An old Enum API that returns a map of symbols to UInts.
@@ -541,7 +590,7 @@ package object Chisel {
     def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = {
       require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
       require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
-      (l zip createValues(l.length)).toMap.asInstanceOf[Map[Symbol, T]]
+      (l.zip(createValues(l.length))).toMap.asInstanceOf[Map[Symbol, T]]
     }
   }
 
@@ -564,16 +613,18 @@ package object Chisel {
     * }}}
     */
   object LFSR16 {
+
     /** Generates a 16-bit linear feedback shift register, returning the register contents.
       * @param increment optional control to gate when the LFSR updates.
       */
     @chiselName
     def apply(increment: Bool = true.B): UInt =
-      VecInit( FibonacciLFSR
-                .maxPeriod(16, increment, seed = Some(BigInt(1) << 15))
-                .asBools
-                .reverse )
-        .asUInt
+      VecInit(
+        FibonacciLFSR
+          .maxPeriod(16, increment, seed = Some(BigInt(1) << 15))
+          .asBools
+          .reverse
+      ).asUInt
 
   }
 
@@ -598,7 +649,6 @@ package object Chisel {
   val Pipe = chisel3.util.Pipe
   type Pipe[T <: Data] = chisel3.util.Pipe[T]
 
-
   /** Package for experimental features, which may have their API changed, be removed, etc.
     *
     * Because its contents won't necessarily have the same level of stability and support as
@@ -638,7 +688,8 @@ package object Chisel {
 
     final def toUInt(implicit compileOptions: CompileOptions): UInt = a.do_asUInt(DeprecatedSourceInfo, compileOptions)
 
-    final def toBools(implicit compileOptions: CompileOptions): Seq[Bool] = a.do_asBools(DeprecatedSourceInfo, compileOptions)
+    final def toBools(implicit compileOptions: CompileOptions): Seq[Bool] =
+      a.do_asBools(DeprecatedSourceInfo, compileOptions)
   }
 
 }
diff --git a/src/main/scala/chisel3/experimental/conversions/package.scala b/src/main/scala/chisel3/experimental/conversions/package.scala
index 574f9f96..7374f223 100644
--- a/src/main/scala/chisel3/experimental/conversions/package.scala
+++ b/src/main/scala/chisel3/experimental/conversions/package.scala
@@ -1,4 +1,3 @@
-
 package chisel3.experimental
 
 import chisel3._
@@ -12,116 +11,229 @@ import scala.language.implicitConversions
 package object conversions {
 
   /** Implicit conversion between `Seq` and `Vec` */
-  implicit def seq2vec[A : DataProduct, B <: Data](xs: Seq[A])(implicit dv: DataView[A, B]): Vec[B] =
+  implicit def seq2vec[A: DataProduct, B <: Data](xs: Seq[A])(implicit dv: DataView[A, B]): Vec[B] =
     xs.viewAs[Vec[B]]
 
   /** Implicit conversion between [[Tuple2]] and [[HWTuple2]] */
-  implicit def tuple2hwtuple[T1 : DataProduct, T2 : DataProduct, V1 <: Data, V2 <: Data](
+  implicit def tuple2hwtuple[T1: DataProduct, T2: DataProduct, V1 <: Data, V2 <: Data](
     tup: (T1, T2)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2]
   ): HWTuple2[V1, V2] = {
     tup.viewAs[HWTuple2[V1, V2]]
   }
 
   /** Implicit conversion between [[Tuple3]] and [[HWTuple3]] */
-  implicit def tuple3hwtuple[T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, V1 <: Data, V2 <: Data, V3 <: Data](
+  implicit def tuple3hwtuple[T1: DataProduct, T2: DataProduct, T3: DataProduct, V1 <: Data, V2 <: Data, V3 <: Data](
     tup: (T1, T2, T3)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3]
   ): HWTuple3[V1, V2, V3] = {
     tup.viewAs[HWTuple3[V1, V2, V3]]
   }
 
   /** Implicit conversion between [[Tuple4]] and [[HWTuple4]] */
   implicit def tuple4hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data
-  ](
-    tup: (T1, T2, T3, T4)
+    T1: DataProduct,
+    T2: DataProduct,
+    T3: DataProduct,
+    T4: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data
+  ](tup: (T1, T2, T3, T4)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4]
   ): HWTuple4[V1, V2, V3, V4] = {
     tup.viewAs[HWTuple4[V1, V2, V3, V4]]
   }
 
   /** Implicit conversion between [[Tuple5]] and [[HWTuple5]] */
   implicit def tuple5hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct, T5 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data, V5 <: Data
-  ](
-    tup: (T1, T2, T3, T4, T5)
+    T1: DataProduct,
+    T2: DataProduct,
+    T3: DataProduct,
+    T4: DataProduct,
+    T5: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data,
+    V5 <: Data
+  ](tup: (T1, T2, T3, T4, T5)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4], v5: DataView[T5, V5]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4],
+    v5:          DataView[T5, V5]
   ): HWTuple5[V1, V2, V3, V4, V5] = {
     tup.viewAs[HWTuple5[V1, V2, V3, V4, V5]]
   }
 
   /** Implicit conversion between [[Tuple6]] and [[HWTuple6]] */
   implicit def tuple6hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct, T5 : DataProduct, T6 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data, V5 <: Data, V6 <: Data
-  ](
-    tup: (T1, T2, T3, T4, T5, T6)
+    T1: DataProduct,
+    T2: DataProduct,
+    T3: DataProduct,
+    T4: DataProduct,
+    T5: DataProduct,
+    T6: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data,
+    V5 <: Data,
+    V6 <: Data
+  ](tup: (T1, T2, T3, T4, T5, T6)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4], v5: DataView[T5, V5],
-             v6: DataView[T6, V6]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4],
+    v5:          DataView[T5, V5],
+    v6:          DataView[T6, V6]
   ): HWTuple6[V1, V2, V3, V4, V5, V6] = {
     tup.viewAs[HWTuple6[V1, V2, V3, V4, V5, V6]]
   }
 
   /** Implicit conversion between [[Tuple7]] and [[HWTuple7]] */
   implicit def tuple7hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct, T5 : DataProduct,
-    T6 : DataProduct, T7 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data, V5 <: Data, V6 <: Data, V7 <: Data
-  ](
-    tup: (T1, T2, T3, T4, T5, T6, T7)
+    T1: DataProduct,
+    T2: DataProduct,
+    T3: DataProduct,
+    T4: DataProduct,
+    T5: DataProduct,
+    T6: DataProduct,
+    T7: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data,
+    V5 <: Data,
+    V6 <: Data,
+    V7 <: Data
+  ](tup: (T1, T2, T3, T4, T5, T6, T7)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4], v5: DataView[T5, V5],
-             v6: DataView[T6, V6], v7: DataView[T7, V7]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4],
+    v5:          DataView[T5, V5],
+    v6:          DataView[T6, V6],
+    v7:          DataView[T7, V7]
   ): HWTuple7[V1, V2, V3, V4, V5, V6, V7] = {
     tup.viewAs[HWTuple7[V1, V2, V3, V4, V5, V6, V7]]
   }
 
   /** Implicit conversion between [[Tuple8]] and [[HWTuple8]] */
   implicit def tuple8hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct, T5 : DataProduct,
-    T6 : DataProduct, T7 : DataProduct, T8 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data, V5 <: Data, V6 <: Data, V7 <: Data, V8 <: Data
-  ](
-    tup: (T1, T2, T3, T4, T5, T6, T7, T8)
+    T1: DataProduct,
+    T2: DataProduct,
+    T3: DataProduct,
+    T4: DataProduct,
+    T5: DataProduct,
+    T6: DataProduct,
+    T7: DataProduct,
+    T8: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data,
+    V5 <: Data,
+    V6 <: Data,
+    V7 <: Data,
+    V8 <: Data
+  ](tup: (T1, T2, T3, T4, T5, T6, T7, T8)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4], v5: DataView[T5, V5],
-    v6: DataView[T6, V6], v7: DataView[T7, V7], v8: DataView[T8, V8]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4],
+    v5:          DataView[T5, V5],
+    v6:          DataView[T6, V6],
+    v7:          DataView[T7, V7],
+    v8:          DataView[T8, V8]
   ): HWTuple8[V1, V2, V3, V4, V5, V6, V7, V8] = {
     tup.viewAs[HWTuple8[V1, V2, V3, V4, V5, V6, V7, V8]]
   }
 
   /** Implicit conversion between [[Tuple9]] and [[HWTuple9]] */
   implicit def tuple9hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct, T5 : DataProduct,
-    T6 : DataProduct, T7 : DataProduct, T8 : DataProduct, T9 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data, V5 <: Data, V6 <: Data, V7 <: Data, V8 <: Data, V9 <: Data
-  ](
-    tup: (T1, T2, T3, T4, T5, T6, T7, T8, T9)
+    T1: DataProduct,
+    T2: DataProduct,
+    T3: DataProduct,
+    T4: DataProduct,
+    T5: DataProduct,
+    T6: DataProduct,
+    T7: DataProduct,
+    T8: DataProduct,
+    T9: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data,
+    V5 <: Data,
+    V6 <: Data,
+    V7 <: Data,
+    V8 <: Data,
+    V9 <: Data
+  ](tup: (T1, T2, T3, T4, T5, T6, T7, T8, T9)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4], v5: DataView[T5, V5],
-    v6: DataView[T6, V6], v7: DataView[T7, V7], v8: DataView[T8, V8], v9: DataView[T9, V9]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4],
+    v5:          DataView[T5, V5],
+    v6:          DataView[T6, V6],
+    v7:          DataView[T7, V7],
+    v8:          DataView[T8, V8],
+    v9:          DataView[T9, V9]
   ): HWTuple9[V1, V2, V3, V4, V5, V6, V7, V8, V9] = {
     tup.viewAs[HWTuple9[V1, V2, V3, V4, V5, V6, V7, V8, V9]]
   }
 
   /** Implicit conversion between [[Tuple10]] and [[HWTuple10]] */
   implicit def tuple10hwtuple[
-    T1 : DataProduct, T2 : DataProduct, T3 : DataProduct, T4 : DataProduct, T5 : DataProduct,
-    T6 : DataProduct, T7 : DataProduct, T8 : DataProduct, T9 : DataProduct, T10 : DataProduct,
-    V1 <: Data, V2 <: Data, V3 <: Data, V4 <: Data, V5 <: Data, V6 <: Data, V7 <: Data, V8 <: Data, V9 <: Data, V10 <: Data
-  ](
-    tup: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10)
+    T1:  DataProduct,
+    T2:  DataProduct,
+    T3:  DataProduct,
+    T4:  DataProduct,
+    T5:  DataProduct,
+    T6:  DataProduct,
+    T7:  DataProduct,
+    T8:  DataProduct,
+    T9:  DataProduct,
+    T10: DataProduct,
+    V1 <: Data,
+    V2 <: Data,
+    V3 <: Data,
+    V4 <: Data,
+    V5 <: Data,
+    V6 <: Data,
+    V7 <: Data,
+    V8 <: Data,
+    V9 <: Data,
+    V10 <: Data
+  ](tup: (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10)
   )(
-    implicit v1: DataView[T1, V1], v2: DataView[T2, V2], v3: DataView[T3, V3], v4: DataView[T4, V4], v5: DataView[T5, V5],
-    v6: DataView[T6, V6], v7: DataView[T7, V7], v8: DataView[T8, V8], v9: DataView[T9, V9], v10: DataView[T10, V10]
+    implicit v1: DataView[T1, V1],
+    v2:          DataView[T2, V2],
+    v3:          DataView[T3, V3],
+    v4:          DataView[T4, V4],
+    v5:          DataView[T5, V5],
+    v6:          DataView[T6, V6],
+    v7:          DataView[T7, V7],
+    v8:          DataView[T8, V8],
+    v9:          DataView[T9, V9],
+    v10:         DataView[T10, V10]
   ): HWTuple10[V1, V2, V3, V4, V5, V6, V7, V8, V9, V10] = {
     tup.viewAs[HWTuple10[V1, V2, V3, V4, V5, V6, V7, V8, V9, V10]]
   }
diff --git a/src/main/scala/chisel3/experimental/verification/package.scala b/src/main/scala/chisel3/experimental/verification/package.scala
index a026542d..1cedb8da 100644
--- a/src/main/scala/chisel3/experimental/verification/package.scala
+++ b/src/main/scala/chisel3/experimental/verification/package.scala
@@ -8,20 +8,44 @@ import chisel3.internal.sourceinfo.SourceInfo
 package object verification {
 
   object assert {
-    @deprecated("Please use chisel3.assert instead. The chisel3.experimental.verification package will be removed.", "Chisel 3.5")
-    def apply(predicate: Bool, msg: String = "")
-      (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): chisel3.assert.Assert = chisel3.assert(predicate, msg)
+    @deprecated(
+      "Please use chisel3.assert instead. The chisel3.experimental.verification package will be removed.",
+      "Chisel 3.5"
+    )
+    def apply(
+      predicate: Bool,
+      msg:       String = ""
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): chisel3.assert.Assert = chisel3.assert(predicate, msg)
   }
 
   object assume {
-    @deprecated("Please use chisel3.assume instead. The chisel3.experimental.verification package will be removed.", "Chisel 3.5")
-    def apply(predicate: Bool, msg: String = "")
-      (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): chisel3.assume.Assume = chisel3.assume(predicate, msg)
+    @deprecated(
+      "Please use chisel3.assume instead. The chisel3.experimental.verification package will be removed.",
+      "Chisel 3.5"
+    )
+    def apply(
+      predicate: Bool,
+      msg:       String = ""
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): chisel3.assume.Assume = chisel3.assume(predicate, msg)
   }
 
   object cover {
-    @deprecated("Please use chisel3.cover instead. The chisel3.experimental.verification package will be removed.", "Chisel 3.5")
-    def apply(predicate: Bool, msg: String = "")
-      (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): chisel3.cover.Cover = chisel3.cover(predicate, msg)
+    @deprecated(
+      "Please use chisel3.cover instead. The chisel3.experimental.verification package will be removed.",
+      "Chisel 3.5"
+    )
+    def apply(
+      predicate: Bool,
+      msg:       String = ""
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): chisel3.cover.Cover = chisel3.cover(predicate, msg)
   }
 }
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index a94558ce..bbf43a45 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -20,4 +20,3 @@ private[chisel3] object Emitter {
     result ++ moduleStrings
   }
 }
-
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index de47ef36..c5811813 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -3,7 +3,15 @@
 package chisel3.stage
 
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
-import firrtl.options.{BufferedCustomFileEmission, CustomFileEmission, HasShellOptions, OptionsException, ShellOption, StageOptions, Unserializable}
+import firrtl.options.{
+  BufferedCustomFileEmission,
+  CustomFileEmission,
+  HasShellOptions,
+  OptionsException,
+  ShellOption,
+  StageOptions,
+  Unserializable
+}
 import firrtl.options.Viewer.view
 import chisel3.{ChiselException, Module}
 import chisel3.RawModule
@@ -29,7 +37,9 @@ case object NoRunFirrtlCompilerAnnotation
       longOption = "no-run-firrtl",
       toAnnotationSeq = _ => Seq(NoRunFirrtlCompilerAnnotation),
       helpText = "Do not run the FIRRTL compiler (generate FIRRTL IR from Chisel and exit)",
-      shortOption = Some("chnrf") ) )
+      shortOption = Some("chnrf")
+    )
+  )
 
 }
 
@@ -45,7 +55,9 @@ case object PrintFullStackTraceAnnotation
     new ShellOption[Unit](
       longOption = "full-stacktrace",
       toAnnotationSeq = _ => Seq(PrintFullStackTraceAnnotation),
-      helpText = "Show full stack trace when an exception is thrown" ) )
+      helpText = "Show full stack trace when an exception is thrown"
+    )
+  )
 
 }
 
@@ -68,15 +80,18 @@ object ChiselGeneratorAnnotation extends HasShellOptions {
     * that Module is found
     */
   def apply(name: String): ChiselGeneratorAnnotation = {
-    val gen = () => try {
-      Class.forName(name).asInstanceOf[Class[_ <: RawModule]].newInstance()
-    } catch {
-      case e: ClassNotFoundException =>
-        throw new OptionsException(s"Unable to locate module '$name'! (Did you misspell it?)", e)
-      case e: InstantiationException =>
-        throw new OptionsException(
-          s"Unable to create instance of module '$name'! (Does this class take parameters?)", e)
-    }
+    val gen = () =>
+      try {
+        Class.forName(name).asInstanceOf[Class[_ <: RawModule]].newInstance()
+      } catch {
+        case e: ClassNotFoundException =>
+          throw new OptionsException(s"Unable to locate module '$name'! (Did you misspell it?)", e)
+        case e: InstantiationException =>
+          throw new OptionsException(
+            s"Unable to create instance of module '$name'! (Does this class take parameters?)",
+            e
+          )
+      }
     ChiselGeneratorAnnotation(gen)
   }
 
@@ -85,17 +100,16 @@ object ChiselGeneratorAnnotation extends HasShellOptions {
       longOption = "module",
       toAnnotationSeq = (a: String) => Seq(ChiselGeneratorAnnotation(a)),
       helpText = "The name of a Chisel module to elaborate (module must be in the classpath)",
-      helpValueName = Some("<package>.<module>") ) )
+      helpValueName = Some("<package>.<module>")
+    )
+  )
 
 }
 
 /** Stores a Chisel Circuit
   * @param circuit a Chisel Circuit
   */
-case class ChiselCircuitAnnotation(circuit: Circuit)
-    extends NoTargetAnnotation
-    with ChiselOption
-    with Unserializable {
+case class ChiselCircuitAnnotation(circuit: Circuit) extends NoTargetAnnotation with ChiselOption with Unserializable {
   /* Caching the hashCode for a large circuit is necessary due to repeated queries.
    * Not caching the hashCode will cause severe performance degredations for large [[Circuit]]s.
    */
@@ -135,8 +149,9 @@ case class CircuitSerializationAnnotation(circuit: Circuit, filename: String, fo
 
   override def getBytesBuffered: Iterable[Array[Byte]] = format match {
     case FirrtlFileFormat =>
-      OldEmitter.emitLazily(circuit)
-                .map(_.getBytes)
+      OldEmitter
+        .emitLazily(circuit)
+        .map(_.getBytes)
     // TODO Use lazy Iterables so that we don't have to materialize full intermediate data structures
     case ProtoBufFileFormat =>
       val ostream = new java.io.ByteArrayOutputStream
@@ -155,7 +170,9 @@ object ChiselOutputFileAnnotation extends HasShellOptions {
       longOption = "chisel-output-file",
       toAnnotationSeq = (a: String) => Seq(ChiselOutputFileAnnotation(a)),
       helpText = "Write Chisel-generated FIRRTL to this file (default: <circuit-main>.fir)",
-      helpValueName = Some("<file>") ) )
+      helpValueName = Some("<file>")
+    )
+  )
 
 }
 
diff --git a/src/main/scala/chisel3/stage/ChiselCli.scala b/src/main/scala/chisel3/stage/ChiselCli.scala
index 8e1974ed..26b032bf 100644
--- a/src/main/scala/chisel3/stage/ChiselCli.scala
+++ b/src/main/scala/chisel3/stage/ChiselCli.scala
@@ -6,9 +6,11 @@ import firrtl.options.Shell
 
 trait ChiselCli { this: Shell =>
   parser.note("Chisel Front End Options")
-  Seq( NoRunFirrtlCompilerAnnotation,
-       PrintFullStackTraceAnnotation,
-       ChiselOutputFileAnnotation,
-       ChiselGeneratorAnnotation )
+  Seq(
+    NoRunFirrtlCompilerAnnotation,
+    PrintFullStackTraceAnnotation,
+    ChiselOutputFileAnnotation,
+    ChiselGeneratorAnnotation
+  )
     .foreach(_.addOptions(parser))
 }
diff --git a/src/main/scala/chisel3/stage/ChiselOptions.scala b/src/main/scala/chisel3/stage/ChiselOptions.scala
index 46a68f64..ed4d0a2f 100644
--- a/src/main/scala/chisel3/stage/ChiselOptions.scala
+++ b/src/main/scala/chisel3/stage/ChiselOptions.scala
@@ -5,22 +5,24 @@ package chisel3.stage
 import chisel3.internal.firrtl.Circuit
 
 class ChiselOptions private[stage] (
-  val runFirrtlCompiler:   Boolean         = true,
-  val printFullStackTrace: Boolean         = false,
-  val outputFile:          Option[String]  = None,
+  val runFirrtlCompiler:   Boolean = true,
+  val printFullStackTrace: Boolean = false,
+  val outputFile:          Option[String] = None,
   val chiselCircuit:       Option[Circuit] = None) {
 
   private[stage] def copy(
-    runFirrtlCompiler:   Boolean         = runFirrtlCompiler,
-    printFullStackTrace: Boolean         = printFullStackTrace,
-    outputFile:          Option[String]  = outputFile,
-    chiselCircuit:       Option[Circuit] = chiselCircuit ): ChiselOptions = {
+    runFirrtlCompiler:   Boolean = runFirrtlCompiler,
+    printFullStackTrace: Boolean = printFullStackTrace,
+    outputFile:          Option[String] = outputFile,
+    chiselCircuit:       Option[Circuit] = chiselCircuit
+  ): ChiselOptions = {
 
     new ChiselOptions(
-      runFirrtlCompiler   = runFirrtlCompiler,
+      runFirrtlCompiler = runFirrtlCompiler,
       printFullStackTrace = printFullStackTrace,
-      outputFile          = outputFile,
-      chiselCircuit       = chiselCircuit )
+      outputFile = outputFile,
+      chiselCircuit = chiselCircuit
+    )
 
   }
 
diff --git a/src/main/scala/chisel3/stage/ChiselPhase.scala b/src/main/scala/chisel3/stage/ChiselPhase.scala
index aa37f3b1..6c7affbc 100644
--- a/src/main/scala/chisel3/stage/ChiselPhase.scala
+++ b/src/main/scala/chisel3/stage/ChiselPhase.scala
@@ -2,28 +2,26 @@
 
 package chisel3.stage
 
-import firrtl.options.{
-  Dependency,
-  Phase,
-  PhaseManager
-}
+import firrtl.options.{Dependency, Phase, PhaseManager}
 import firrtl.options.phases.DeletedWrapper
 
 private[chisel3] class ChiselPhase extends PhaseManager(ChiselPhase.targets) {
 
-  override val wrappers = Seq( (a: Phase) => DeletedWrapper(a) )
+  override val wrappers = Seq((a: Phase) => DeletedWrapper(a))
 
 }
 
 private[chisel3] object ChiselPhase {
 
   val targets: Seq[PhaseManager.PhaseDependency] =
-    Seq( Dependency[chisel3.stage.phases.Checks],
-         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
-         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
-         Dependency[chisel3.stage.phases.MaybeAspectPhase],
-         Dependency[chisel3.stage.phases.AddSerializationAnnotations],
-         Dependency[chisel3.stage.phases.Convert],
-         Dependency[chisel3.stage.phases.MaybeFirrtlStage] )
+    Seq(
+      Dependency[chisel3.stage.phases.Checks],
+      Dependency[chisel3.stage.phases.AddImplicitOutputFile],
+      Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
+      Dependency[chisel3.stage.phases.MaybeAspectPhase],
+      Dependency[chisel3.stage.phases.AddSerializationAnnotations],
+      Dependency[chisel3.stage.phases.Convert],
+      Dependency[chisel3.stage.phases.MaybeFirrtlStage]
+    )
 
 }
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 0c76f411..1224a8f1 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -22,7 +22,7 @@ import chisel3.{ChiselException, RawModule}
 import chisel3.internal.{firrtl => cir, ErrorLog}
 import chisel3.stage.CircuitSerializationAnnotation.FirrtlFileFormat
 
-import java.io.{StringWriter, PrintWriter}
+import java.io.{PrintWriter, StringWriter}
 
 class ChiselStage extends Stage {
 
@@ -51,17 +51,16 @@ class ChiselStage extends Stage {
     * @return a string containing the Verilog output
     */
   final def emitChirrtl(
-    gen: => RawModule,
-    args: Array[String] = Array.empty,
-    annotations: AnnotationSeq = Seq.empty): String = {
+    gen:         => RawModule,
+    args:        Array[String] = Array.empty,
+    annotations: AnnotationSeq = Seq.empty
+  ): String = {
 
     val annos = execute(Array("--no-run-firrtl") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
 
-    annos
-      .collectFirst {
-        case a: ChiselCircuitAnnotation => CircuitSerializationAnnotation(a.circuit, "", FirrtlFileFormat).getBytes
-      }
-      .get
+    annos.collectFirst {
+      case a: ChiselCircuitAnnotation => CircuitSerializationAnnotation(a.circuit, "", FirrtlFileFormat).getBytes
+    }.get
       .map(_.toChar)
       .mkString
 
@@ -74,15 +73,15 @@ class ChiselStage extends Stage {
     * @return a string containing the FIRRTL output
     */
   final def emitFirrtl(
-    gen: => RawModule,
-    args: Array[String] = Array.empty,
-    annotations: AnnotationSeq = Seq.empty): String = {
-
-    execute(Array("-X", "high") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
-      .collect {
-        case EmittedFirrtlCircuitAnnotation(a) => a
-        case EmittedFirrtlModuleAnnotation(a)  => a
-      }.map(_.value)
+    gen:         => RawModule,
+    args:        Array[String] = Array.empty,
+    annotations: AnnotationSeq = Seq.empty
+  ): String = {
+
+    execute(Array("-X", "high") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations).collect {
+      case EmittedFirrtlCircuitAnnotation(a) => a
+      case EmittedFirrtlModuleAnnotation(a)  => a
+    }.map(_.value)
       .mkString("")
 
   }
@@ -94,15 +93,15 @@ class ChiselStage extends Stage {
     * @return a string containing the Verilog output
     */
   final def emitVerilog(
-    gen: => RawModule,
-    args: Array[String] = Array.empty,
-    annotations: AnnotationSeq = Seq.empty): String = {
-
-    execute(Array("-X", "verilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
-      .collectFirst {
-        case EmittedVerilogCircuitAnnotation(a) => a
-        case EmittedVerilogModuleAnnotation(a)  => a
-      }.map(_.value)
+    gen:         => RawModule,
+    args:        Array[String] = Array.empty,
+    annotations: AnnotationSeq = Seq.empty
+  ): String = {
+
+    execute(Array("-X", "verilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations).collectFirst {
+      case EmittedVerilogCircuitAnnotation(a) => a
+      case EmittedVerilogModuleAnnotation(a)  => a
+    }.map(_.value)
       .mkString("")
 
   }
@@ -114,15 +113,15 @@ class ChiselStage extends Stage {
     * @return a string containing the SystemVerilog output
     */
   final def emitSystemVerilog(
-                         gen: => RawModule,
-                         args: Array[String] = Array.empty,
-                         annotations: AnnotationSeq = Seq.empty): String = {
-
-    execute(Array("-X", "sverilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations)
-      .collectFirst {
-        case EmittedVerilogCircuitAnnotation(a) => a
-        case EmittedVerilogModuleAnnotation(a)  => a
-      }.map(_.value)
+    gen:         => RawModule,
+    args:        Array[String] = Array.empty,
+    annotations: AnnotationSeq = Seq.empty
+  ): String = {
+
+    execute(Array("-X", "sverilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations).collectFirst {
+      case EmittedVerilogCircuitAnnotation(a) => a
+      case EmittedVerilogModuleAnnotation(a)  => a
+    }.map(_.value)
       .mkString("")
 
   }
@@ -138,8 +137,7 @@ object ChiselStage {
     */
   def elaborate(gen: => RawModule): cir.Circuit = {
     val phase = new ChiselPhase {
-      override val targets = Seq( Dependency[chisel3.stage.phases.Checks],
-                                  Dependency[chisel3.stage.phases.Elaborate] )
+      override val targets = Seq(Dependency[chisel3.stage.phases.Checks], Dependency[chisel3.stage.phases.Elaborate])
     }
 
     phase
@@ -161,7 +159,8 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
         Dependency[chisel3.stage.phases.MaybeAspectPhase],
-        Dependency[chisel3.stage.phases.Convert] )
+        Dependency[chisel3.stage.phases.Convert]
+      )
     }
 
     phase
@@ -181,7 +180,8 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.AddImplicitOutputFile],
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
         Dependency[chisel3.stage.phases.MaybeAspectPhase],
-        Dependency[chisel3.stage.phases.Convert] )
+        Dependency[chisel3.stage.phases.Convert]
+      )
     }
 
     phase
@@ -209,14 +209,16 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
         Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert],
-        Dependency[firrtl.stage.phases.Compiler] )
+        Dependency[firrtl.stage.phases.Compiler]
+      )
     )
 
     phase
       .transform(Seq(ChiselGeneratorAnnotation(() => gen), RunFirrtlTransformAnnotation(new HighFirrtlEmitter)))
       .collectFirst {
         case EmittedFirrtlCircuitAnnotation(a) => a
-      }.get
+      }
+      .get
       .value
 
   }
@@ -233,14 +235,16 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
         Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert],
-        Dependency[firrtl.stage.phases.Compiler] )
+        Dependency[firrtl.stage.phases.Compiler]
+      )
     )
 
     phase
       .transform(Seq(ChiselGeneratorAnnotation(() => gen), RunFirrtlTransformAnnotation(new VerilogEmitter)))
       .collectFirst {
         case EmittedVerilogCircuitAnnotation(a) => a
-      }.get
+      }
+      .get
       .value
   }
 
@@ -256,14 +260,16 @@ object ChiselStage {
         Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
         Dependency[chisel3.stage.phases.MaybeAspectPhase],
         Dependency[chisel3.stage.phases.Convert],
-        Dependency[firrtl.stage.phases.Compiler] )
+        Dependency[firrtl.stage.phases.Compiler]
+      )
     )
 
     phase
       .transform(Seq(ChiselGeneratorAnnotation(() => gen), RunFirrtlTransformAnnotation(new SystemVerilogEmitter)))
       .collectFirst {
         case EmittedVerilogCircuitAnnotation(a) => a
-      }.get
+      }
+      .get
       .value
   }
 
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala
index c307d3ae..bf03e2df 100644
--- a/src/main/scala/chisel3/stage/package.scala
+++ b/src/main/scala/chisel3/stage/package.scala
@@ -12,14 +12,13 @@ package object stage {
 
   implicit object ChiselOptionsView extends OptionsView[ChiselOptions] {
 
-    def view(options: AnnotationSeq): ChiselOptions = options
-      .collect { case a: ChiselOption => a }
-      .foldLeft(new ChiselOptions()){ (c, x) =>
+    def view(options: AnnotationSeq): ChiselOptions = options.collect { case a: ChiselOption => a }
+      .foldLeft(new ChiselOptions()) { (c, x) =>
         x match {
           case _: NoRunFirrtlCompilerAnnotation.type => c.copy(runFirrtlCompiler = false)
           case _: PrintFullStackTraceAnnotation.type => c.copy(printFullStackTrace = true)
-          case ChiselOutputFileAnnotation(f)         => c.copy(outputFile = Some(f))
-          case ChiselCircuitAnnotation(a)            => c.copy(chiselCircuit = Some(a))
+          case ChiselOutputFileAnnotation(f) => c.copy(outputFile = Some(f))
+          case ChiselCircuitAnnotation(a)    => c.copy(chiselCircuit = Some(a))
         }
       }
 
diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
index 3ce9dacd..6874e2a2 100644
--- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
+++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
@@ -16,15 +16,16 @@ class AddImplicitOutputAnnotationFile extends Phase {
   override def optionalPrerequisiteOf = Seq.empty
   override def invalidates(a: Phase) = false
 
-  def transform(annotations: AnnotationSeq): AnnotationSeq = annotations
-    .collectFirst{ case _: OutputAnnotationFileAnnotation => annotations }
-    .getOrElse{
+  def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.collectFirst {
+    case _: OutputAnnotationFileAnnotation => annotations
+  }.getOrElse {
 
-      val x: Option[AnnotationSeq] = annotations
-        .collectFirst{ case a: ChiselCircuitAnnotation =>
-          OutputAnnotationFileAnnotation(a.circuit.name) +: annotations }
-
-      x.getOrElse(annotations)
+    val x: Option[AnnotationSeq] = annotations.collectFirst {
+      case a: ChiselCircuitAnnotation =>
+        OutputAnnotationFileAnnotation(a.circuit.name) +: annotations
     }
 
+    x.getOrElse(annotations)
+  }
+
 }
diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
index e39d4d54..2507c2c8 100644
--- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
+++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
@@ -18,11 +18,12 @@ class AddImplicitOutputFile extends Phase {
   override def invalidates(a: Phase) = false
 
   def transform(annotations: AnnotationSeq): AnnotationSeq =
-    annotations.collectFirst{ case _: ChiselOutputFileAnnotation  => annotations }.getOrElse{
+    annotations.collectFirst { case _: ChiselOutputFileAnnotation => annotations }.getOrElse {
 
-      val x: Option[AnnotationSeq] = annotations
-        .collectFirst{ case a: ChiselCircuitAnnotation =>
-          ChiselOutputFileAnnotation(a.circuit.name) +: annotations }
+      val x: Option[AnnotationSeq] = annotations.collectFirst {
+        case a: ChiselCircuitAnnotation =>
+          ChiselOutputFileAnnotation(a.circuit.name) +: annotations
+      }
 
       x.getOrElse(annotations)
     }
diff --git a/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala b/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
index 93425b07..d35b2f2e 100644
--- a/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
+++ b/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
@@ -22,7 +22,9 @@ class AddSerializationAnnotations extends Phase {
   def transform(annotations: AnnotationSeq): AnnotationSeq = {
     val chiselOptions = view[ChiselOptions](annotations)
     val circuit = chiselOptions.chiselCircuit.getOrElse {
-      throw new ChiselException(s"Unable to locate the elaborated circuit, did ${classOf[Elaborate].getName} run correctly")
+      throw new ChiselException(
+        s"Unable to locate the elaborated circuit, did ${classOf[Elaborate].getName} run correctly"
+      )
     }
     val baseFilename = chiselOptions.outputFile.getOrElse(circuit.name)
 
diff --git a/src/main/scala/chisel3/stage/phases/AspectPhase.scala b/src/main/scala/chisel3/stage/phases/AspectPhase.scala
index 72965861..efe2c3a4 100644
--- a/src/main/scala/chisel3/stage/phases/AspectPhase.scala
+++ b/src/main/scala/chisel3/stage/phases/AspectPhase.scala
@@ -28,7 +28,7 @@ class AspectPhase extends Phase {
         Nil
       case other => Seq(other)
     }
-    if(dut.isDefined) {
+    if (dut.isDefined) {
       val newAnnotations = aspects.flatMap { _.resolveAspect(dut.get, remainingAnnotations) }
       remainingAnnotations ++ newAnnotations
     } else annotations
diff --git a/src/main/scala/chisel3/stage/phases/Checks.scala b/src/main/scala/chisel3/stage/phases/Checks.scala
index 1ff7f64c..55c90ccb 100644
--- a/src/main/scala/chisel3/stage/phases/Checks.scala
+++ b/src/main/scala/chisel3/stage/phases/Checks.scala
@@ -31,21 +31,24 @@ class Checks extends Phase {
       throw new OptionsException(
         s"""|At most one NoRunFirrtlCompilerAnnotation can be specified, but found '${noF.size}'. Did you duplicate:
             |    - option or annotation: -chnrf, --no-run-firrtl, NoRunFirrtlCompilerAnnotation
-            |""".stripMargin)
+            |""".stripMargin
+      )
     }
 
     if (st.size > 1) {
       throw new OptionsException(
         s"""|At most one PrintFullStackTraceAnnotation can be specified, but found '${noF.size}'. Did you duplicate:
             |    - option or annotation: --full-stacktrace, PrintFullStackTraceAnnotation
-            |""".stripMargin)
+            |""".stripMargin
+      )
     }
 
     if (outF.size > 1) {
       throw new OptionsException(
         s"""|At most one Chisel output file can be specified but found '${outF.size}'. Did you duplicate:
             |    - option or annotation: --chisel-output-file, ChiselOutputFileAnnotation
-            |""".stripMargin)
+            |""".stripMargin
+      )
     }
 
     annotations
diff --git a/src/main/scala/chisel3/stage/phases/Convert.scala b/src/main/scala/chisel3/stage/phases/Convert.scala
index b5b01b8d..014ed3f2 100644
--- a/src/main/scala/chisel3/stage/phases/Convert.scala
+++ b/src/main/scala/chisel3/stage/phases/Convert.scala
@@ -24,20 +24,13 @@ class Convert extends Phase {
   def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {
     case a: ChiselCircuitAnnotation =>
       Some(a) ++
-      /* Convert this Chisel Circuit to a FIRRTL Circuit */
-      Some(FirrtlCircuitAnnotation(Converter.convert(a.circuit))) ++
-      /* Convert all Chisel Annotations to FIRRTL Annotations */
-      a
-        .circuit
-        .firrtlAnnotations ++
-      a
-        .circuit
-        .annotations
-        .collect {
+        /* Convert this Chisel Circuit to a FIRRTL Circuit */
+        Some(FirrtlCircuitAnnotation(Converter.convert(a.circuit))) ++
+        /* Convert all Chisel Annotations to FIRRTL Annotations */
+        a.circuit.firrtlAnnotations ++
+        a.circuit.annotations.collect {
           case anno: RunFirrtlTransform => anno.transformClass
-        }
-        .distinct
-        .map { c: Class[_ <: Transform] => RunFirrtlTransformAnnotation(c.newInstance()) }
+        }.distinct.map { c: Class[_ <: Transform] => RunFirrtlTransformAnnotation(c.newInstance()) }
     case a => Some(a)
   }
 
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala
index e8f2623e..2cfb3200 100644
--- a/src/main/scala/chisel3/stage/phases/Elaborate.scala
+++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala
@@ -20,18 +20,19 @@ class Elaborate extends Phase {
   override def invalidates(a: Phase) = false
 
   def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.flatMap {
-    case ChiselGeneratorAnnotation(gen) => try {
-          val (circuit, dut) = Builder.build(Module(gen()), new DynamicContext(annotations))
-          Seq(ChiselCircuitAnnotation(circuit), DesignAnnotation(dut))
-    } catch {
-      /* if any throwable comes back and we're in "stack trace trimming" mode, then print an error and trim the stack trace
-       */
-      case scala.util.control.NonFatal(a) =>
-        if (!view[ChiselOptions](annotations).printFullStackTrace) {
-          a.trimStackTraceToUserCode()
-        }
-        throw(a)
-    }
+    case ChiselGeneratorAnnotation(gen) =>
+      try {
+        val (circuit, dut) = Builder.build(Module(gen()), new DynamicContext(annotations))
+        Seq(ChiselCircuitAnnotation(circuit), DesignAnnotation(dut))
+      } catch {
+        /* if any throwable comes back and we're in "stack trace trimming" mode, then print an error and trim the stack trace
+         */
+        case scala.util.control.NonFatal(a) =>
+          if (!view[ChiselOptions](annotations).printFullStackTrace) {
+            a.trimStackTraceToUserCode()
+          }
+          throw (a)
+      }
     case a => Some(a)
   }
 
diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala
index 756c5db4..254f8add 100644
--- a/src/main/scala/chisel3/stage/phases/Emitter.scala
+++ b/src/main/scala/chisel3/stage/phases/Emitter.scala
@@ -25,10 +25,12 @@ import java.io.{File, FileWriter}
 class Emitter extends Phase {
 
   override def prerequisites =
-    Seq( Dependency[Elaborate],
-         Dependency[AddImplicitOutputFile],
-         Dependency[AddImplicitOutputAnnotationFile],
-         Dependency[MaybeAspectPhase] )
+    Seq(
+      Dependency[Elaborate],
+      Dependency[AddImplicitOutputFile],
+      Dependency[AddImplicitOutputAnnotationFile],
+      Dependency[MaybeAspectPhase]
+    )
   override def optionalPrerequisites = Seq.empty
   override def optionalPrerequisiteOf = Seq(Dependency[Convert])
   override def invalidates(a: Phase) = false
diff --git a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala
index c26cbd82..dcd0dfe0 100644
--- a/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala
+++ b/src/main/scala/chisel3/stage/phases/MaybeAspectPhase.scala
@@ -16,7 +16,7 @@ class MaybeAspectPhase extends Phase {
   override def invalidates(a: Phase) = false
 
   def transform(annotations: AnnotationSeq): AnnotationSeq = {
-    if(annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) {
+    if (annotations.collectFirst { case a: Aspect[_] => annotations }.isDefined) {
       new AspectPhase().transform(annotations)
     } else annotations
   }
diff --git a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
index cd68e04c..3533d8d1 100644
--- a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
+++ b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
@@ -17,8 +17,8 @@ class MaybeFirrtlStage extends Phase {
   override def optionalPrerequisiteOf = Seq.empty
   override def invalidates(a: Phase) = false
 
-  def transform(annotations: AnnotationSeq): AnnotationSeq = annotations
-    .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations }
-    .getOrElse    { (new FirrtlStage).transform(annotations)          }
+  def transform(annotations: AnnotationSeq): AnnotationSeq = annotations.collectFirst {
+    case NoRunFirrtlCompilerAnnotation => annotations
+  }.getOrElse { (new FirrtlStage).transform(annotations) }
 
 }
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 99002660..5e28a523 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -13,7 +13,7 @@ class BasicTester extends Module() {
   // The testbench has no IOs, rather it should communicate using printf, assert, and stop.
   val io = IO(new Bundle() {})
 
-  def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
+  def popCount(n: Long): Int = n.toBinaryString.count(_ == '1')
 
   /** Ends the test reporting success.
     *
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index e87aceca..9c4b2da9 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -16,24 +16,27 @@ import firrtl.transforms.BlackBoxSourceHelper.writeResourceToDirectory
 object TesterDriver extends BackendCompilationUtilities {
 
   private[chisel3] trait Backend extends NoTargetAnnotation with Unserializable {
-    def execute(t: () => BasicTester,
-                additionalVResources: Seq[String] = Seq(),
-                annotations: AnnotationSeq = Seq(),
-                nameHint:    Option[String] = None
-               ): Boolean
+    def execute(
+      t:                    () => BasicTester,
+      additionalVResources: Seq[String] = Seq(),
+      annotations:          AnnotationSeq = Seq(),
+      nameHint:             Option[String] = None
+    ): Boolean
   }
   case object VerilatorBackend extends Backend {
+
     /** For use with modules that should successfully be elaborated by the
-      * frontend, and which can be turned into executables with assertions. */
-    def execute(t: () => BasicTester,
-                additionalVResources: Seq[String] = Seq(),
-                annotations: AnnotationSeq = Seq(),
-                nameHint:    Option[String] = None
-               ): Boolean = {
+      * frontend, and which can be turned into executables with assertions.
+      */
+    def execute(
+      t:                    () => BasicTester,
+      additionalVResources: Seq[String] = Seq(),
+      annotations:          AnnotationSeq = Seq(),
+      nameHint:             Option[String] = None
+    ): Boolean = {
       val pm = new PhaseManager(
-        targets = Seq(Dependency[AddImplicitTesterDirectory],
-                      Dependency[Emitter],
-                      Dependency[Convert]))
+        targets = Seq(Dependency[AddImplicitTesterDirectory], Dependency[Emitter], Dependency[Convert])
+      )
 
       val annotationsx = pm.transform(ChiselGeneratorAnnotation(finishWrapper(t)) +: annotations)
 
@@ -41,7 +44,7 @@ object TesterDriver extends BackendCompilationUtilities {
       val path = annotationsx.collectFirst { case TargetDirAnnotation(dir) => dir }.map(new File(_)).get
 
       // Copy CPP harness and other Verilog sources from resources into files
-      val cppHarness =  new File(path, "top.cpp")
+      val cppHarness = new File(path, "top.cpp")
       copyResourceToFile("/chisel3/top.cpp", cppHarness)
       // NOTE: firrtl.Driver.execute() may end up copying these same resources in its BlackBoxSourceHelper code.
       // As long as the same names are used for the output files, and we avoid including duplicate files
@@ -54,8 +57,10 @@ object TesterDriver extends BackendCompilationUtilities {
       (new FirrtlStage).execute(Array("--compiler", "verilog"), annotationsx)
 
       // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-      if ((verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
-          cppToExe(target, path)).! == 0) {
+      if (
+        (verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+          cppToExe(target, path)).! == 0
+      ) {
         executeExpectingSuccess(target, path)
       } else {
         false
@@ -77,21 +82,26 @@ object TesterDriver extends BackendCompilationUtilities {
     override def invalidates(a: Phase) = false
 
     override def transform(a: AnnotationSeq) = a.flatMap {
-      case a@ ChiselCircuitAnnotation(circuit) =>
-        Seq(a, TargetDirAnnotation(
-              firrtl.util.BackendCompilationUtilities.createTestDirectory(circuit.name)
-                .getAbsolutePath
-                .toString))
+      case a @ ChiselCircuitAnnotation(circuit) =>
+        Seq(
+          a,
+          TargetDirAnnotation(
+            firrtl.util.BackendCompilationUtilities.createTestDirectory(circuit.name).getAbsolutePath.toString
+          )
+        )
       case a => Seq(a)
     }
   }
 
   /** For use with modules that should successfully be elaborated by the
-    * frontend, and which can be turned into executables with assertions. */
-  def execute(t:                    () => BasicTester,
-              additionalVResources: Seq[String] = Seq(),
-              annotations:          AnnotationSeq = Seq(),
-              nameHint:             Option[String] = None): Boolean = {
+    * frontend, and which can be turned into executables with assertions.
+    */
+  def execute(
+    t:                    () => BasicTester,
+    additionalVResources: Seq[String] = Seq(),
+    annotations:          AnnotationSeq = Seq(),
+    nameHint:             Option[String] = None
+  ): Boolean = {
 
     val backendAnnotations = annotations.collect { case anno: Backend => anno }
     val backendAnnotation = if (backendAnnotations.length == 1) {
@@ -109,11 +119,11 @@ object TesterDriver extends BackendCompilationUtilities {
     * The finish method is a hook for code that augments the circuit built in the constructor.
     */
   def finishWrapper(test: () => BasicTester): () => BasicTester = { () =>
-  {
-    val tester = test()
-    tester.finish()
-    tester
-  }
+    {
+      val tester = test()
+      tester.finish()
+      tester
+    }
   }
 
 }
diff --git a/src/main/scala/chisel3/testers/package.scala b/src/main/scala/chisel3/testers/package.scala
index f60f7cc2..f20a7977 100644
--- a/src/main/scala/chisel3/testers/package.scala
+++ b/src/main/scala/chisel3/testers/package.scala
@@ -3,8 +3,5 @@
 package chisel3
 
 /** The testers package provides the basic interface for chisel testers.
-  *
   */
-package object testers {
-
-}
+package object testers {}
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index b68acae1..220a12b1 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -6,7 +6,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs
   * (selects) at most one.
@@ -18,20 +18,22 @@ import chisel3.internal.naming.chiselName  // can't use chisel3_ version because
 class ArbiterIO[T <: Data](private val gen: T, val n: Int) extends Bundle {
   // See github.com/freechipsproject/chisel3/issues/765 for why gen is a private val and proposed replacement APIs.
 
-/** Input data, one per potential sender
-  * 
-  * @group Signals
-  */
-  val in  = Flipped(Vec(n, Decoupled(gen)))
-/** Output data after arbitration
-  *
-  * @group Signals
-  */
+  /** Input data, one per potential sender
+    *
+    * @group Signals
+    */
+  val in = Flipped(Vec(n, Decoupled(gen)))
+
+  /** Output data after arbitration
+    *
+    * @group Signals
+    */
   val out = Decoupled(gen)
-/** One-Hot vector indicating which output was chosen
-  *
-  * @group Signals
-  */
+
+  /** One-Hot vector indicating which output was chosen
+    *
+    * @group Signals
+    */
   val chosen = Output(UInt(log2Ceil(n).W))
 }
 
@@ -46,7 +48,7 @@ private object ArbiterCtrl {
 }
 
 abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
-  def grant: Seq[Bool]
+  def grant:  Seq[Bool]
   def choice: UInt
   val io = IO(new ArbiterIO(gen, n))
 
@@ -60,16 +62,16 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
     val locked = lockCount.value =/= 0.U
     val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(true.B)
 
-    when (io.out.fire && wantsLock) {
+    when(io.out.fire && wantsLock) {
       lockIdx := io.chosen
       lockCount.inc()
     }
 
-    when (locked) { io.chosen := lockIdx }
-    for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
+    when(locked) { io.chosen := lockIdx }
+    for ((in, (g, i)) <- io.in.zip(grant.zipWithIndex))
       in.ready := Mux(locked, lockIdx === i.asUInt, g) && io.out.ready
   } else {
-    for ((in, g) <- io.in zip grant)
+    for ((in, g) <- io.in.zip(grant))
       in.ready := g && io.out.ready
   }
 }
@@ -78,27 +80,27 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   lazy val lastGrant = RegEnable(io.chosen, io.out.fire)
   lazy val grantMask = (0 until n).map(_.asUInt > lastGrant)
-  lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
+  lazy val validMask = io.in.zip(grantMask).map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
     val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid))
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = WireDefault((n-1).asUInt)
-  for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := i.asUInt }
-  for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := i.asUInt }
+  override lazy val choice = WireDefault((n - 1).asUInt)
+  for (i <- n - 2 to 0 by -1)
+    when(io.in(i).valid) { choice := i.asUInt }
+  for (i <- n - 1 to 1 by -1)
+    when(validMask(i)) { choice := i.asUInt }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = WireDefault((n-1).asUInt)
-  for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := i.asUInt }
+  override lazy val choice = WireDefault((n - 1).asUInt)
+  for (i <- n - 2 to 0 by -1)
+    when(io.in(i).valid) { choice := i.asUInt }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -133,17 +135,17 @@ class RRArbiter[T <: Data](val gen: T, val n: Int) extends LockingRRArbiter[T](g
 class Arbiter[T <: Data](val gen: T, val n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := (n-1).asUInt
-  io.out.bits := io.in(n-1).bits
-  for (i <- n-2 to 0 by -1) {
-    when (io.in(i).valid) {
+  io.chosen := (n - 1).asUInt
+  io.out.bits := io.in(n - 1).bits
+  for (i <- n - 2 to 0 by -1) {
+    when(io.in(i).valid) {
       io.chosen := i.asUInt
       io.out.bits := io.in(i).bits
     }
   }
 
   val grant = ArbiterCtrl(io.in.map(_.valid))
-  for ((in, g) <- io.in zip grant)
+  for ((in, g) <- io.in.zip(grant))
     in.ready := g && io.out.ready
   io.out.valid := !grant.last || io.in.last.valid
 }
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 808245de..d27fee14 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -6,12 +6,11 @@ import scala.language.experimental.macros
 import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
-
 object BitPat {
 
   private[chisel3] implicit val bitPatOrder = new Ordering[BitPat] {
     import scala.math.Ordered.orderingToOrdered
-    def compare(x: BitPat, y: BitPat): Int = (x.getWidth, x.value, x.mask) compare (y.getWidth, y.value, y.mask)
+    def compare(x: BitPat, y: BitPat): Int = (x.getWidth, x.value, x.mask).compare(y.getWidth, y.value, y.mask)
   }
 
   /** Parses a bit pattern string into (bits, mask, width).
@@ -33,7 +32,7 @@ object BitPat {
     var mask = BigInt(0)
     var count = 0
     for (d <- x.tail) {
-      if (! (d == '_' || d.isWhitespace)) {
+      if (!(d == '_' || d.isWhitespace)) {
         require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d)
         mask = (mask << 1) + (if (d == '?') 0 else 1)
         bits = (bits << 1) + (if (d == '1') 1 else 0)
@@ -105,15 +104,14 @@ object BitPat {
 
     import scala.language.experimental.macros
 
-    final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-    final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def ===(that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def =/=(that: BitPat): Bool = macro SourceInfoTransform.thatArg
 
     /** @group SourceInfoTransformMacro */
-    def do_=== (that: BitPat)
-               (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x
+    def do_===(that: BitPat)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x
+
     /** @group SourceInfoTransformMacro */
-    def do_=/= (that: BitPat)
-               (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x
+    def do_=/=(that: BitPat)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x
   }
 }
 
@@ -148,6 +146,7 @@ package experimental {
 
   /** A Set of [[BitPat]] represents a set of bit vector with mask. */
   sealed trait BitSet { outer =>
+
     /** all [[BitPat]] elements in [[terms]] make up this [[BitSet]].
       * all [[terms]] should be have the same width.
       */
@@ -229,7 +228,6 @@ package experimental {
 
 }
 
-
 /** Bit patterns are literals with masks, used to represent values with don't
   * care bits. Equality comparisons will ignore don't care bits.
   *
@@ -239,7 +237,9 @@ package experimental {
   * "b10001".U === BitPat("b101??") // evaluates to false.B
   * }}}
   */
-sealed class BitPat(val value: BigInt, val mask: BigInt, val width: Int) extends util.experimental.BitSet with SourceInfoDoc {
+sealed class BitPat(val value: BigInt, val mask: BigInt, val width: Int)
+    extends util.experimental.BitSet
+    with SourceInfoDoc {
   import chisel3.util.experimental.BitSet
   def terms = Set(this)
 
@@ -247,11 +247,11 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, val width: Int) extends
     * Get specified width of said BitPat
     */
   override def getWidth: Int = width
-  def apply(x: Int): BitPat = macro SourceInfoTransform.xArg
-  def apply(x: Int, y: Int): BitPat = macro SourceInfoTransform.xyArg
-  def === (that: UInt): Bool = macro SourceInfoTransform.thatArg
-  def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
-  def ## (that: BitPat): BitPat = macro SourceInfoTransform.thatArg
+  def apply(x:  Int): BitPat = macro SourceInfoTransform.xArg
+  def apply(x:  Int, y: Int): BitPat = macro SourceInfoTransform.xyArg
+  def ===(that: UInt):   Bool = macro SourceInfoTransform.thatArg
+  def =/=(that: UInt):   Bool = macro SourceInfoTransform.thatArg
+  def ##(that:  BitPat): BitPat = macro SourceInfoTransform.thatArg
 
   /** @group SourceInfoTransformMacro */
   def do_apply(x: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): BitPat = {
@@ -266,15 +266,15 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, val width: Int) extends
   }
 
   /** @group SourceInfoTransformMacro */
-  def do_=== (that: UInt)
-      (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
+  def do_===(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     value.asUInt === (that & mask.asUInt)
   }
+
   /** @group SourceInfoTransformMacro */
-  def do_=/= (that: UInt)
-      (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
+  def do_=/=(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     !(this === that)
   }
+
   /** @group SourceInfoTransformMacro */
   def do_##(that: BitPat)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): BitPat = {
     new BitPat((value << that.getWidth) + that.value, (mask << that.getWidth) + that.mask, this.width + that.getWidth)
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index ddf7546a..0d8318bf 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -19,6 +19,7 @@ import chisel3._
   * }}}
   */
 object FillInterleaved {
+
   /** Creates n repetitions of each bit of x in order.
     *
     * Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times)
@@ -58,6 +59,7 @@ object PopCount {
   * }}}
   */
 object Fill {
+
   /** Create n repetitions of x using a tree fanout topology.
     *
     * Output data-equivalent to x ## x ## ... ## x (n repetitions).
@@ -66,8 +68,8 @@ object Fill {
   def apply(n: Int, x: UInt): UInt = {
     n match {
       case _ if n < 0 => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
-      case 0 => UInt(0.W)
-      case 1 => x
+      case 0          => UInt(0.W)
+      case 1          => x
       case _ if x.isWidthKnown && x.getWidth == 1 =>
         Mux(x.asBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
       case _ =>
@@ -75,7 +77,7 @@ object Fill {
         val p2 = Array.ofDim[UInt](nBits)
         p2(0) = x
         for (i <- 1 until p2.length)
-          p2(i) = Cat(p2(i-1), p2(i-1))
+          p2(i) = Cat(p2(i - 1), p2(i - 1))
         Cat((0 until nBits).filter(i => (n & (1 << i)) != 0).map(p2(_)))
     }
   }
@@ -91,22 +93,22 @@ object Fill {
   */
 object Reverse {
   private def doit(in: UInt, length: Int): UInt = length match {
-    case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
-    case _ if length <= 1 => in
+    case _ if length < 0                                    => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
+    case _ if length <= 1                                   => in
     case _ if isPow2(length) && length >= 8 && length <= 64 =>
       // This esoterica improves simulation performance
       var res = in
       var shift = length >> 1
       var mask = ((BigInt(1) << length) - 1).asUInt(length.W)
       do {
-        mask = mask ^ (mask(length-shift-1,0) << shift)
-        res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
+        mask = mask ^ (mask(length - shift - 1, 0) << shift)
+        res = ((res >> shift) & mask) | ((res(length - shift - 1, 0) << shift) & ~mask)
         shift = shift >> 1
       } while (shift > 0)
       res
     case _ =>
-      val half = (1 << log2Ceil(length))/2
-      Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half))
+      val half = (1 << log2Ceil(length)) / 2
+      Cat(doit(in(half - 1, 0), half), doit(in(length - 1, half), length - half))
   }
 
   def apply(in: UInt): UInt = doit(in, in.getWidth)
diff --git a/src/main/scala/chisel3/util/BlackBoxUtils.scala b/src/main/scala/chisel3/util/BlackBoxUtils.scala
index 443d7f3e..7c4400f8 100644
--- a/src/main/scala/chisel3/util/BlackBoxUtils.scala
+++ b/src/main/scala/chisel3/util/BlackBoxUtils.scala
@@ -4,14 +4,20 @@ package chisel3.util
 
 import chisel3._
 import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform}
-import firrtl.transforms.{BlackBoxPathAnno, BlackBoxResourceAnno, BlackBoxInlineAnno, BlackBoxSourceHelper,
-  BlackBoxNotFoundException}
+import firrtl.transforms.{
+  BlackBoxInlineAnno,
+  BlackBoxNotFoundException,
+  BlackBoxPathAnno,
+  BlackBoxResourceAnno,
+  BlackBoxSourceHelper
+}
 import firrtl.annotations.ModuleName
 import logger.LazyLogging
 
 private[util] object BlackBoxHelpers {
 
   implicit class BlackBoxInlineAnnoHelpers(anno: BlackBoxInlineAnno.type) extends LazyLogging {
+
     /** Generate a BlackBoxInlineAnno from a Java Resource and a module name. */
     def fromResource(resourceName: String, moduleName: ModuleName) = try {
       val blackBoxFile = os.resource / os.RelPath(resourceName.dropWhile(_ == '/'))
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index 3369eb18..c5adce56 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -15,6 +15,7 @@ import chisel3._
   * }}}
   */
 object Cat {
+
   /** Concatenates the argument data elements, in argument order, together. The first argument
     * forms the most significant bits, while the last argument forms the least significant bits.
     */
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 58961630..df60f059 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -6,7 +6,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** Returns the base-2 integer logarithm of an UInt.
   *
@@ -17,9 +17,9 @@ import chisel3.internal.naming.chiselName  // can't use chisel3_ version because
   * Log2(13.U)  // evaluates to 3.U (truncation)
   * Log2(myUIntWire)
   * }}}
-  *
   */
 object Log2 {
+
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     */
   @chiselName
@@ -29,11 +29,11 @@ object Log2 {
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), (width-1).asUInt, apply(x, width-1))
+      Mux(x(width - 1), (width - 1).asUInt, apply(x, width - 1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
-      val hi = x(width-1, mid)
-      val lo = x(mid-1, 0)
+      val hi = x(width - 1, mid)
+      val lo = x(mid - 1, 0)
       val useHi = hi.orR
       Cat(useHi, Mux(useHi, Log2(hi, width - mid), Log2(lo, mid)))
     }
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 1ac94bfe..754112eb 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -17,7 +17,13 @@ import chisel3.internal.sourceinfo.SourceInfo
   * @note DO NOT USE. This API is subject to change without warning.
   */
 class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lits: Set[BigInt]) {
-  def is(v: Iterable[T])(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SwitchContext[T] = {
+  def is(
+    v:     Iterable[T]
+  )(block: => Any
+  )(
+    implicit sourceInfo: SourceInfo,
+    compileOptions:      CompileOptions
+  ): SwitchContext[T] = {
     if (!v.isEmpty) {
       val newLits = v.map { w =>
         require(w.litOption.isDefined, "is condition must be literal")
@@ -26,17 +32,25 @@ class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lit
         value
       }
       // def instead of val so that logic ends up in legal place
-      def p = v.map(_.asUInt === cond.asUInt).reduce(_||_)
+      def p = v.map(_.asUInt === cond.asUInt).reduce(_ || _)
       whenContext match {
         case Some(w) => new SwitchContext(cond, Some(w.elsewhen(p)(block)), lits ++ newLits)
-        case None => new SwitchContext(cond, Some(when(p)(block)), lits ++ newLits)
+        case None    => new SwitchContext(cond, Some(when(p)(block)), lits ++ newLits)
       }
     } else {
       this
     }
   }
-  def is(v: T)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SwitchContext[T] = is(Seq(v))(block)
-  def is(v: T, vr: T*)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SwitchContext[T] = is(v :: vr.toList)(block)
+  def is(v: T)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SwitchContext[T] =
+    is(Seq(v))(block)
+  def is(
+    v:     T,
+    vr:    T*
+  )(block: => Any
+  )(
+    implicit sourceInfo: SourceInfo,
+    compileOptions:      CompileOptions
+  ): SwitchContext[T] = is(v :: vr.toList)(block)
 }
 
 /** Use to specify cases in a [[switch]] block, equivalent to a [[when$ when]] block comparing to
@@ -84,15 +98,17 @@ object is {
   */
 object switch {
   def apply[T <: Element](cond: T)(x: => Any): Unit = macro impl
-  def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
+  def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = {
+    import c.universe._
     val q"..$body" = x
     val res = body.foldLeft(q"""new chisel3.util.SwitchContext($cond, None, Set.empty)""") {
-      case (acc, tree) => tree match {
-        // TODO: remove when Chisel compatibility package is removed
-        case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
-        case q"chisel3.util.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
-        case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
-      }
+      case (acc, tree) =>
+        tree match {
+          // TODO: remove when Chisel compatibility package is removed
+          case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
+          case q"chisel3.util.is.apply( ..$params )( ..$body )"     => q"$acc.is( ..$params )( ..$body )"
+          case b                                                    => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
+        }
     }
     q"""{ $res }"""
   }
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 5910c703..ef1eff9f 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -3,7 +3,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** Used to generate an inline (logic directly in the containing Module, no internal Module is created)
   * hardware counter.
@@ -42,11 +42,13 @@ class Counter private (r: Range, oldN: Option[Int] = None) {
     */
   def n: Int = oldN match {
     case Some(x) => x
-    case None =>
+    case None    =>
       // Reasonable for typical ranges
-      require(r.start == 0 && r.step == 1,
+      require(
+        r.start == 0 && r.step == 1,
         s"Counter.n only defined on ranges starting at 0 with step == 1, got $r. " +
-        "Use underlying range.")
+          "Use underlying range."
+      )
       r.last + 1
   }
 
@@ -98,14 +100,14 @@ class Counter private (r: Range, oldN: Option[Int] = None) {
   }
 }
 
-object Counter
-{
+object Counter {
+
   /** Instantiate a [[Counter! counter]] with the specified number of counts.
     */
   def apply(n: Int): Counter = new Counter(n)
 
   /** Instantiate a [[Counter! counter]] with the specified number of counts and a gate.
-   *
+    *
     * @param cond condition that controls whether the counter increments this cycle
     * @param n number of counts before the counter resets
     * @return tuple of the counter value and whether the counter will wrap (the value is at
@@ -115,7 +117,7 @@ object Counter
   def apply(cond: Bool, n: Int): (UInt, Bool) = {
     val c = new Counter(n)
     val wrap = WireInit(false.B)
-    when (cond) { wrap := c.inc() }
+    when(cond) { wrap := c.inc() }
     (c.value, wrap)
   }
 
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 4b8b3eeb..5c71a4ea 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -6,8 +6,8 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction, requireIsChiselType}
-import chisel3.internal.naming._  // can't use chisel3_ version because of compile order
+import chisel3.experimental.{requireIsChiselType, DataMirror, Direction}
+import chisel3.internal.naming._ // can't use chisel3_ version because of compile order
 
 /** An I/O Bundle containing 'valid' and 'ready' signals that handshake
   * the transfer of data stored in the 'bits' subfield.
@@ -18,40 +18,41 @@ import chisel3.internal.naming._  // can't use chisel3_ version because of compi
   * @param gen the type of data to be wrapped in Ready/Valid
   * @groupdesc Signals The actual hardware fields of the Bundle
   */
-abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
-{
+abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: Module))
-        if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
+    case (true, Some(module: Module)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }
 
-/** Indicates that the consumer is ready to accept the data this cycle
-  * @group Signals
-  */
+  /** Indicates that the consumer is ready to accept the data this cycle
+    * @group Signals
+    */
   val ready = Input(Bool())
-  
-/** Indicates that the producer has put valid data in 'bits' 
-  * @group Signals
-  */
+
+  /** Indicates that the producer has put valid data in 'bits'
+    * @group Signals
+    */
   val valid = Output(Bool())
-  
-/** The data to be transferred when ready and valid are asserted at the same cycle
-  * @group Signals
-  */
-  val bits  = Output(genType)
+
+  /** The data to be transferred when ready and valid are asserted at the same cycle
+    * @group Signals
+    */
+  val bits = Output(genType)
 }
 
 object ReadyValidIO {
 
-  implicit class AddMethodsToReadyValid[T<:Data](target: ReadyValidIO[T]) {
+  implicit class AddMethodsToReadyValid[T <: Data](target: ReadyValidIO[T]) {
 
     /** Indicates if IO is both ready and valid
-     */
+      */
     def fire: Bool = target.ready && target.valid
 
-    @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+    @deprecated(
+      "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead",
+      "Chisel 3.5"
+    )
     def fire(dummy: Int = 0): Bool = fire
 
     /** Push dat onto the output bits of this interface to let the consumer know it has happened.
@@ -99,8 +100,8 @@ object ReadyValidIO {
 class DecoupledIO[+T <: Data](gen: T) extends ReadyValidIO[T](gen)
 
 /** This factory adds a decoupled handshaking protocol to a data bundle. */
-object Decoupled
-{
+object Decoupled {
+
   /** Wraps some Data with a DecoupledIO interface. */
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
 
@@ -110,6 +111,7 @@ object Decoupled
   // Both of these methods return DecoupledIO parameterized by the most generic type: Data
   /** Returns a [[DecoupledIO]] inteface with no payload */
   def apply(): DecoupledIO[Data] = apply(new EmptyBundle)
+
   /** Returns a [[DecoupledIO]] inteface with no payload */
   def empty: DecoupledIO[Data] = Decoupled()
 
@@ -119,7 +121,10 @@ object Decoupled
     */
   @chiselName
   def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
-    require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.")
+    require(
+      DataMirror.directionOf(irr.bits) == Direction.Output,
+      "Only safe to cast produced Irrevocable bits to Decoupled."
+    )
     val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits)))
     d.bits := irr.bits
     d.valid := irr.valid
@@ -138,8 +143,7 @@ object Decoupled
 class IrrevocableIO[+T <: Data](gen: T) extends ReadyValidIO[T](gen)
 
 /** Factory adds an irrevocable handshaking protocol to a data bundle. */
-object Irrevocable
-{
+object Irrevocable {
   def apply[T <: Data](gen: T): IrrevocableIO[T] = new IrrevocableIO(gen)
 
   /** Upconverts a DecoupledIO input to an IrrevocableIO, allowing an IrrevocableIO to be used
@@ -148,7 +152,10 @@ object Irrevocable
     * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO
     */
   def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = {
-    require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.")
+    require(
+      DataMirror.directionOf(dec.bits) == Direction.Input,
+      "Only safe to cast consumed Decoupled bits to Irrevocable."
+    )
     val i = Wire(new IrrevocableIO(chiselTypeOf(dec.bits)))
     dec.bits := i.bits
     dec.valid := i.valid
@@ -161,13 +168,14 @@ object Irrevocable
   * @param gen The type of data to enqueue
   */
 object EnqIO {
-  def apply[T<:Data](gen: T): DecoupledIO[T] = Decoupled(gen)
+  def apply[T <: Data](gen: T): DecoupledIO[T] = Decoupled(gen)
 }
+
 /** Consumer - drives (outputs) ready, inputs valid and bits.
   * @param gen The type of data to dequeue
   */
 object DeqIO {
-  def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(Decoupled(gen))
+  def apply[T <: Data](gen: T): DecoupledIO[T] = Flipped(Decoupled(gen))
 }
 
 /** An I/O Bundle for Queues
@@ -176,28 +184,34 @@ object DeqIO {
   * @param hasFlush A boolean for whether the generated Queue is flushable
   * @groupdesc Signals The hardware fields of the Bundle
   */
-class QueueIO[T <: Data](private val gen: T, val entries: Int, val hasFlush: Boolean = false) extends Bundle
-{ // See github.com/freechipsproject/chisel3/issues/765 for why gen is a private val and proposed replacement APIs.
+class QueueIO[T <: Data](
+  private val gen: T,
+  val entries:     Int,
+  val hasFlush:    Boolean = false)
+    extends Bundle { // See github.com/freechipsproject/chisel3/issues/765 for why gen is a private val and proposed replacement APIs.
 
   /* These may look inverted, because the names (enq/deq) are from the perspective of the client,
    *  but internally, the queue implementation itself sits on the other side
    *  of the interface so uses the flipped instance.
    */
-  /** I/O to enqueue data (client is producer, and Queue object is consumer), is [[Chisel.DecoupledIO]] flipped. 
+  /** I/O to enqueue data (client is producer, and Queue object is consumer), is [[Chisel.DecoupledIO]] flipped.
     * @group Signals
     */
   val enq = Flipped(EnqIO(gen))
+
   /** I/O to dequeue data (client is consumer and Queue object is producer), is [[Chisel.DecoupledIO]]
     * @group Signals
     */
   val deq = Flipped(DeqIO(gen))
-  /** The current amount of data in the queue 
+
+  /** The current amount of data in the queue
     * @group Signals
     */
   val count = Output(UInt(log2Ceil(entries + 1).W))
+
   /** When asserted, reset the enqueue and dequeue pointers, effectively flushing the queue (Optional IO for a flushable Queue)
     * @group Signals
-    */ 
+    */
   val flush = if (hasFlush) Some(Input(Bool())) else None
 
 }
@@ -218,13 +232,15 @@ class QueueIO[T <: Data](private val gen: T, val entries: Int, val hasFlush: Boo
   * }}}
   */
 @chiselName
-class Queue[T <: Data](val gen: T,
-                       val entries: Int,
-                       val pipe: Boolean = false,
-                       val flow: Boolean = false,
-                       val useSyncReadMem: Boolean = false, 
-                       val hasFlush: Boolean = false)
-                      (implicit compileOptions: chisel3.CompileOptions)
+class Queue[T <: Data](
+  val gen:            T,
+  val entries:        Int,
+  val pipe:           Boolean = false,
+  val flow:           Boolean = false,
+  val useSyncReadMem: Boolean = false,
+  val hasFlush:       Boolean = false
+)(
+  implicit compileOptions: chisel3.CompileOptions)
     extends Module() {
   require(entries > -1, "Queue must have non-negative number of entries")
   require(entries != 0, "Use companion object Queue.apply for zero entries")
@@ -253,21 +269,21 @@ class Queue[T <: Data](val gen: T,
 
   // when flush is high, empty the queue
   // Semantically, any enqueues happen before the flush.
-  when (do_enq) {
+  when(do_enq) {
     ram(enq_ptr.value) := io.enq.bits
     enq_ptr.inc()
   }
-  when (do_deq) {
+  when(do_deq) {
     deq_ptr.inc()
   }
-  when (do_enq =/= do_deq) {
+  when(do_enq =/= do_deq) {
     maybe_full := do_enq
   }
   when(flush) {
     enq_ptr.reset()
     deq_ptr.reset()
     maybe_full := false.B
-  }  
+  }
 
   io.deq.valid := !empty
   io.enq.ready := !full
@@ -276,22 +292,21 @@ class Queue[T <: Data](val gen: T,
     val deq_ptr_next = Mux(deq_ptr.value === (entries.U - 1.U), 0.U, deq_ptr.value + 1.U)
     val r_addr = WireDefault(Mux(do_deq, deq_ptr_next, deq_ptr.value))
     io.deq.bits := ram.read(r_addr)
-  }
-  else {
+  } else {
     io.deq.bits := ram(deq_ptr.value)
   }
 
   if (flow) {
-    when (io.enq.valid) { io.deq.valid := true.B }
-    when (empty) {
+    when(io.enq.valid) { io.deq.valid := true.B }
+    when(empty) {
       io.deq.bits := io.enq.bits
       do_deq := false.B
-      when (io.deq.ready) { do_enq := false.B }
+      when(io.deq.ready) { do_enq := false.B }
     }
   }
 
   if (pipe) {
-    when (io.deq.ready) { io.enq.ready := true.B }
+    when(io.deq.ready) { io.enq.ready := true.B }
   }
 
   val ptr_diff = enq_ptr.value - deq_ptr.value
@@ -299,17 +314,17 @@ class Queue[T <: Data](val gen: T,
   if (isPow2(entries)) {
     io.count := Mux(maybe_full && ptr_match, entries.U, 0.U) | ptr_diff
   } else {
-    io.count := Mux(ptr_match,
-                    Mux(maybe_full,
-                      entries.asUInt, 0.U),
-                    Mux(deq_ptr.value > enq_ptr.value,
-                      entries.asUInt + ptr_diff, ptr_diff))
+    io.count := Mux(
+      ptr_match,
+      Mux(maybe_full, entries.asUInt, 0.U),
+      Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)
+    )
   }
 }
 
 /** Factory for a generic hardware queue. */
-object Queue
-{
+object Queue {
+
   /** Create a [[Queue]] and supply a [[DecoupledIO]] containing the product.
     *
     * @param enq input (enqueue) interface to the queue, also determines type of queue elements.
@@ -329,12 +344,13 @@ object Queue
     */
   @chiselName
   def apply[T <: Data](
-      enq: ReadyValidIO[T],
-      entries: Int = 2,
-      pipe: Boolean = false,
-      flow: Boolean = false,
-      useSyncReadMem: Boolean = false,
-      flush: Option[Bool] = None): DecoupledIO[T] = {
+    enq:            ReadyValidIO[T],
+    entries:        Int = 2,
+    pipe:           Boolean = false,
+    flow:           Boolean = false,
+    useSyncReadMem: Boolean = false,
+    flush:          Option[Bool] = None
+  ): DecoupledIO[T] = {
     if (entries == 0) {
       val deq = Wire(new DecoupledIO(chiselTypeOf(enq.bits)))
       deq.valid := enq.valid
@@ -373,12 +389,13 @@ object Queue
     */
   @chiselName
   def irrevocable[T <: Data](
-      enq: ReadyValidIO[T],
-      entries: Int = 2,
-      pipe: Boolean = false,
-      flow: Boolean = false,
-      useSyncReadMem: Boolean = false,
-      flush: Option[Bool] = None): IrrevocableIO[T] = {
+    enq:            ReadyValidIO[T],
+    entries:        Int = 2,
+    pipe:           Boolean = false,
+    flow:           Boolean = false,
+    useSyncReadMem: Boolean = false,
+    flush:          Option[Bool] = None
+  ): IrrevocableIO[T] = {
     val deq = apply(enq, entries, pipe, flow, useSyncReadMem, flush)
     require(entries > 0, "Zero-entry queues don't guarantee Irrevocability")
     val irr = Wire(new IrrevocableIO(chiselTypeOf(deq.bits)))
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 4501a2de..059506d9 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -26,9 +26,10 @@ import chisel3._
   * }}}
   */
 trait Enum {
+
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
   protected def createValues(n: Int): Seq[UInt] =
-    (0 until n).map(_.U((1 max log2Ceil(n)).W))
+    (0 until n).map(_.U((1.max(log2Ceil(n))).W))
 
   /** Returns n unique UInt values
     *
diff --git a/src/main/scala/chisel3/util/ExtModuleUtils.scala b/src/main/scala/chisel3/util/ExtModuleUtils.scala
index 62f384bc..5c9c02ba 100644
--- a/src/main/scala/chisel3/util/ExtModuleUtils.scala
+++ b/src/main/scala/chisel3/util/ExtModuleUtils.scala
@@ -3,8 +3,13 @@
 package chisel3.util
 
 import chisel3.experimental.{ChiselAnnotation, ExtModule, RunFirrtlTransform}
-import firrtl.transforms.{BlackBoxPathAnno, BlackBoxResourceAnno, BlackBoxInlineAnno, BlackBoxSourceHelper,
-  BlackBoxNotFoundException}
+import firrtl.transforms.{
+  BlackBoxInlineAnno,
+  BlackBoxNotFoundException,
+  BlackBoxPathAnno,
+  BlackBoxResourceAnno,
+  BlackBoxSourceHelper
+}
 
 import BlackBoxHelpers._
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 792280ac..99d567ad 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -12,6 +12,6 @@ import scala.language.implicitConversions
 object ImplicitConversions {
   // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
   // UInt.asUInt.
-  implicit def intToUInt(x: Int): UInt = chisel3.fromIntToLiteral(x).asUInt
+  implicit def intToUInt(x:     Int):     UInt = chisel3.fromIntToLiteral(x).asUInt
   implicit def booleanToBool(x: Boolean): Bool = x.B
 }
diff --git a/src/main/scala/chisel3/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala
index e0ed694f..f538c4d1 100644
--- a/src/main/scala/chisel3/util/Lookup.scala
+++ b/src/main/scala/chisel3/util/Lookup.scala
@@ -29,8 +29,9 @@ import chisel3._
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
     val map = mapping.map(m => (m._1 === addr, m._2))
-    default.zipWithIndex map { case (d, i) =>
-      map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n))
+    default.zipWithIndex.map {
+      case (d, i) =>
+        map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n))
     }
   }
 }
diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index 2a833e80..6eab9241 100644
--- a/src/main/scala/chisel3/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -47,7 +47,7 @@ object log2Up {
 object log2Ceil {
   def apply(in: BigInt): Int = {
     require(in > 0)
-    (in-1).bitLength
+    (in - 1).bitLength
   }
   def apply(in: Int): Int = apply(BigInt(in))
 }
@@ -82,7 +82,7 @@ object log2Down {
   */
 object log2Floor {
   def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1)
-  def apply(in: Int): Int = apply(BigInt(in))
+  def apply(in: Int):    Int = apply(BigInt(in))
 }
 
 /** Returns whether a Scala integer is a power of two.
@@ -95,12 +95,12 @@ object log2Floor {
   * }}}
   */
 object isPow2 {
-  def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
-  def apply(in: Int): Boolean = apply(BigInt(in))
+  def apply(in: BigInt): Boolean = in > 0 && ((in & (in - 1)) == 0)
+  def apply(in: Int):    Boolean = apply(BigInt(in))
 }
 
-
 object unsignedBitLength {
+
   /** Return the number of bits required to encode a specific value, assuming no sign bit is required.
     *
     * Basically, `n.bitLength`. NOTE: This will return 0 for a value of 0.
@@ -115,6 +115,7 @@ object unsignedBitLength {
 }
 
 object signedBitLength {
+
   /** Return the number of bits required to encode a specific value, assuming a sign bit is required.
     *
     * Basically, 0 for 0, 1 for -1, and `n.bitLength` + 1 for everything else.
@@ -124,9 +125,9 @@ object signedBitLength {
     */
   def apply(in: BigInt): Int = {
     in.toInt match {
-      case 0 => 0
+      case 0  => 0
       case -1 => 1
-      case _ => in.bitLength + 1
+      case _  => in.bitLength + 1
     }
 
   }
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala
index 14d6be38..5f8c9da8 100644
--- a/src/main/scala/chisel3/util/MixedVec.scala
+++ b/src/main/scala/chisel3/util/MixedVec.scala
@@ -19,6 +19,7 @@ import scala.collection.immutable.ListMap
   * }}}
   */
 object MixedVecInit {
+
   /**
     * Create a MixedVec wire from a Seq of values.
     */
@@ -45,6 +46,7 @@ object MixedVecInit {
   * @return MixedVec with the given types.
   */
 object MixedVec {
+
   /**
     * Create a MixedVec type from a Seq of Chisel types.
     */
@@ -111,7 +113,7 @@ final class MixedVec[T <: Data](private val eltsIn: Seq[T]) extends Record with
     */
   def :=(that: Seq[T]): Unit = {
     require(this.length == that.length)
-    for ((a, b) <- this zip that)
+    for ((a, b) <- this.zip(that))
       a := b
   }
 
diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
index 946de461..e84b86a4 100644
--- a/src/main/scala/chisel3/util/Mux.scala
+++ b/src/main/scala/chisel3/util/Mux.scala
@@ -23,8 +23,8 @@ import chisel3._
   */
 object Mux1H {
   def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T =
-    apply(sel zip in)
-  def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in)
+    apply(sel.zip(in))
+  def apply[T <: Data](in:  Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in)
   def apply[T <: Data](sel: UInt, in: Seq[T]): T =
     apply((0 until in.size).map(sel(_)), in)
   def apply(sel: UInt, in: UInt): Bool = (sel & in).orR
@@ -44,8 +44,8 @@ object Mux1H {
   * Returns the output of the Mux tree.
   */
 object PriorityMux {
-  def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
-  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in)
+  def apply[T <: Data](in:  Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
+  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel.zip(in))
   def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
 }
 
@@ -57,12 +57,13 @@ object PriorityMux {
   * }}}
   */
 object MuxLookup {
+
   /** @param key a key to search for
     * @param default a default value if nothing is found
     * @param mapping a sequence to search of keys and values
     * @return the value found or the default if not
     */
-  def apply[S <: UInt, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = {
+  def apply[S <: UInt, T <: Data](key: S, default: T, mapping: Seq[(S, T)]): T = {
     /* If the mapping is defined for all possible values of the key, then don't use the default value */
     val (defaultx, mappingx) = key.widthOption match {
       case Some(width) =>
@@ -77,7 +78,7 @@ object MuxLookup {
       case None => (default, mapping)
     }
 
-    mappingx.foldLeft(defaultx){ case (d, (k, v)) => Mux(k === key, v, d) }
+    mappingx.foldLeft(defaultx) { case (d, (k, v)) => Mux(k === key, v, d) }
   }
 }
 
@@ -89,12 +90,14 @@ object MuxLookup {
   * }}}
   */
 object MuxCase {
+
   /** @param default the default value if none are enabled
     * @param mapping a set of data values with associated enables
-    * @return the first value in mapping that is enabled */
-  def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
+    * @return the first value in mapping that is enabled
+    */
+  def apply[T <: Data](default: T, mapping: Seq[(Bool, T)]): T = {
     var res = default
-    for ((t, v) <- mapping.reverse){
+    for ((t, v) <- mapping.reverse) {
       res = Mux(t, v, res)
     }
     res
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 03f470c7..23b350e5 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -20,15 +20,15 @@ import chisel3._
 object OHToUInt {
   def apply(in: Seq[Bool]): UInt = apply(Cat(in.reverse), in.size)
   def apply(in: Vec[Bool]): UInt = apply(in.asUInt, in.size)
-  def apply(in: Bits): UInt = apply(in, in.getWidth)
+  def apply(in: Bits):      UInt = apply(in, in.getWidth)
 
   def apply(in: Bits, width: Int): UInt = {
     if (width <= 2) {
       Log2(in, width)
     } else {
-      val mid = 1 << (log2Ceil(width)-1)
-      val hi = in(width-1, mid)
-      val lo = in(mid-1, 0)
+      val mid = 1 << (log2Ceil(width) - 1)
+      val hi = in(width - 1, mid)
+      val lo = in(mid - 1, 0)
       Cat(hi.orR, apply(hi | lo, mid))
     }
   }
@@ -44,7 +44,7 @@ object OHToUInt {
   */
 object PriorityEncoder {
   def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(_.asUInt))
-  def apply(in: Bits): UInt = apply(in.asBools)
+  def apply(in: Bits):      UInt = apply(in.asBools)
 }
 
 /** Returns the one hot encoding of the input UInt.
@@ -52,7 +52,6 @@ object PriorityEncoder {
   * @example {{{
   * UIntToOH(2.U) // results in "b0100".U
   * }}}
-  *
   */
 object UIntToOH {
   def apply(in: UInt): UInt = 1.U << in
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index e2b5d172..ddb74dd6 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -5,6 +5,7 @@ package chisel3.util
 import chisel3._
 
 object RegEnable {
+
   /** Returns a register with the specified next, update enable gate, and no reset initialization.
     *
     * @example {{{
@@ -13,7 +14,7 @@ object RegEnable {
     */
   def apply[T <: Data](next: T, enable: Bool): T = {
     val r = Reg(chiselTypeOf(next))
-    when (enable) { r := next }
+    when(enable) { r := next }
     r
   }
 
@@ -25,13 +26,13 @@ object RegEnable {
     */
   def apply[T <: Data](next: T, init: T, enable: Bool): T = {
     val r = RegInit(init)
-    when (enable) { r := next }
+    when(enable) { r := next }
     r
   }
 }
 
-object ShiftRegister
-{
+object ShiftRegister {
+
   /** Returns the n-cycle delayed version of the input signal.
     *
     * @param in input to delay
@@ -55,18 +56,17 @@ object ShiftRegister
     * val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena)
     * }}}
     */
-  def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T = ShiftRegisters(in, n, resetData, en).lastOption.getOrElse(in)
+  def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T =
+    ShiftRegisters(in, n, resetData, en).lastOption.getOrElse(in)
 }
 
+object ShiftRegisters {
 
-object ShiftRegisters
-{
   /** Returns a sequence of delayed input signal registers from 1 to n.
     *
     * @param in input to delay
     * @param n  number of cycles to delay
     * @param en enable the shift
-    *
     */
   def apply[T <: Data](in: T, n: Int, en: Bool = true.B): Seq[T] =
     Seq.iterate(in, n + 1)(util.RegEnable(_, en)).drop(1)
@@ -77,7 +77,6 @@ object ShiftRegisters
     * @param n         number of cycles to delay
     * @param resetData reset value for each register in the shift
     * @param en        enable the shift
-    *
     */
   def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): Seq[T] =
     Seq.iterate(in, n + 1)(util.RegEnable(_, resetData, en)).drop(1)
diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala
index 97c13696..cc8f2456 100644
--- a/src/main/scala/chisel3/util/TransitName.scala
+++ b/src/main/scala/chisel3/util/TransitName.scala
@@ -42,24 +42,23 @@ object TransitName {
     * @param to the thing that will receive the "good" name
     * @return the `from` parameter
     */
-  def apply[T<:HasId](from: T, to: HasId): T = {
+  def apply[T <: HasId](from: T, to: HasId): T = {
     // To transit a name, we need to hook on both the suggestName and autoSeed mechanisms
-    from.addSuggestPostnameHook((given_name: String) => {to.suggestName(given_name)})
-    from.addAutoPostnameHook((given_name: String) => {to.autoSeed(given_name)})
+    from.addSuggestPostnameHook((given_name: String) => { to.suggestName(given_name) })
+    from.addAutoPostnameHook((given_name: String) => { to.autoSeed(given_name) })
     from
   }
 
-
   /** Transit a name from one type to another ''and add a suffix''
     * @param suffix the suffix to append
     * @param from the thing with a "good" name
     * @param to the thing that will receive the "good" name
     * @return the `from` parameter
     */
-  def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = {
+  def withSuffix[T <: HasId](suffix: String)(from: T, to: HasId): T = {
     // To transit a name, we need to hook on both the suggestName and autoSeed mechanisms
-    from.addSuggestPostnameHook((given_name: String) => {to.suggestName(given_name + suffix)})
-    from.addAutoPostnameHook((given_name: String) => {to.autoSeed(given_name + suffix)})
+    from.addSuggestPostnameHook((given_name: String) => { to.suggestName(given_name + suffix) })
+    from.addAutoPostnameHook((given_name: String) => { to.autoSeed(given_name + suffix) })
     from
   }
 
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 5d80502a..eeb2ab68 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -20,7 +20,8 @@ import chisel3._
   * @groupdesc Signals The actual hardware fields of the Bundle
   */
 class Valid[+T <: Data](gen: T) extends Bundle {
-  /** A bit that will be asserted when `bits` is valid 
+
+  /** A bit that will be asserted when `bits` is valid
     * @group Signals
     */
   val valid = Output(Bool())
@@ -28,14 +29,17 @@ class Valid[+T <: Data](gen: T) extends Bundle {
   /** The data to be transferred, qualified by `valid`
     * @group Signals
     */
-  val bits  = Output(gen)
+  val bits = Output(gen)
 
   /** True when `valid` is asserted
     * @return a Chisel [[Bool]] true if `valid` is asserted
     */
   def fire: Bool = valid
 
-  @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+  @deprecated(
+    "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead",
+    "Chisel 3.5"
+  )
   def fire(dummy: Int = 0): Bool = valid
 }
 
@@ -122,7 +126,7 @@ object Pipe {
     } else {
       val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
-      val out = apply(v, b, latency-1)(compileOptions)
+      val out = apply(v, b, latency - 1)(compileOptions)
 
       TransitName.withSuffix("Pipe_valid")(out, v)
       TransitName.withSuffix("Pipe_bits")(out, b)
@@ -182,12 +186,12 @@ class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions:
     */
   class PipeIO extends Bundle {
 
-    /** [[Valid]] input 
+    /** [[Valid]] input
       * @group Signals
       */
     val enq = Input(Valid(gen))
 
-    /** [[Valid]] output. Data will appear here `latency` cycles after being valid at `enq`. 
+    /** [[Valid]] output. Data will appear here `latency` cycles after being valid at `enq`.
       * @group Signals
       */
     val deq = Output(Valid(gen))
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index f2a3e757..254f83a4 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -3,11 +3,11 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate}
+import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.internal.{InstanceId, NamedComponent, Namespace}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
-import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
-import firrtl.annotations.{ModuleName, ComponentName}
+import firrtl.passes.wiring.{SinkAnnotation, SourceAnnotation, WiringTransform}
+import firrtl.annotations.{ComponentName, ModuleName}
 
 import scala.concurrent.SyncVar
 
@@ -122,20 +122,25 @@ object BoringUtils {
     * @note if a uniqueName is not specified, the returned name may differ from the user-provided name
     */
   def addSource(
-    component: NamedComponent,
-    name: String,
+    component:    NamedComponent,
+    name:         String,
     disableDedup: Boolean = false,
-    uniqueName: Boolean = false): String = {
+    uniqueName:   Boolean = false
+  ): String = {
 
-    val id = if (uniqueName) { newName(name) } else { name }
+    val id = if (uniqueName) { newName(name) }
+    else { name }
     val maybeDedup =
       if (disableDedup) { Seq(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(component.toNamed.module) }) }
-      else              { Seq[ChiselAnnotation]()                                                                  }
+      else { Seq[ChiselAnnotation]() }
     val annotations =
-      Seq(new ChiselAnnotation with RunFirrtlTransform {
-            def toFirrtl = SourceAnnotation(component.toNamed, id)
-            def transformClass = classOf[WiringTransform] },
-          new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(component.toNamed) } ) ++ maybeDedup
+      Seq(
+        new ChiselAnnotation with RunFirrtlTransform {
+          def toFirrtl = SourceAnnotation(component.toNamed, id)
+          def transformClass = classOf[WiringTransform]
+        },
+        new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(component.toNamed) }
+      ) ++ maybeDedup
 
     annotations.foreach(annotate(_))
     id
@@ -150,25 +155,28 @@ object BoringUtils {
     * @throws BoringUtilsException if name is expected to exist and it doesn't
     */
   def addSink(
-    component: InstanceId,
-    name: String,
+    component:    InstanceId,
+    name:         String,
     disableDedup: Boolean = false,
-    forceExists: Boolean = false): Unit = {
+    forceExists:  Boolean = false
+  ): Unit = {
 
     if (forceExists && !checkName(name)) {
-      throw new BoringUtilsException(s"Sink ID '$name' not found in BoringUtils ID namespace") }
+      throw new BoringUtilsException(s"Sink ID '$name' not found in BoringUtils ID namespace")
+    }
     def moduleName = component.toNamed match {
-      case c: ModuleName => c
+      case c: ModuleName    => c
       case c: ComponentName => c.module
       case _ => throw new ChiselException("Can only add a Module or Component sink", null)
     }
     val maybeDedup =
       if (disableDedup) { Seq(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(moduleName) }) }
-      else              { Seq[ChiselAnnotation]()                                                    }
+      else { Seq[ChiselAnnotation]() }
     val annotations =
       Seq(new ChiselAnnotation with RunFirrtlTransform {
-            def toFirrtl = SinkAnnotation(component.toNamed, name)
-            def transformClass = classOf[WiringTransform] }) ++ maybeDedup
+        def toFirrtl = SinkAnnotation(component.toNamed, name)
+        def transformClass = classOf[WiringTransform]
+      }) ++ maybeDedup
     annotations.foreach(annotate(_))
   }
 
@@ -181,11 +189,12 @@ object BoringUtils {
     * component
     */
   def bore(source: Data, sinks: Seq[Data]): String = {
-    val boringName = try {
-      source.instanceName
-    } catch {
-      case _: Exception => "bore"
-    }
+    val boringName =
+      try {
+        source.instanceName
+      } catch {
+        case _: Exception => "bore"
+      }
     val genName = addSource(source, boringName, true, true)
     sinks.foreach(addSink(_, genName, true, true))
     genName
diff --git a/src/main/scala/chisel3/util/experimental/ForceNames.scala b/src/main/scala/chisel3/util/experimental/ForceNames.scala
index bac69ed4..53ee2bd2 100644
--- a/src/main/scala/chisel3/util/experimental/ForceNames.scala
+++ b/src/main/scala/chisel3/util/experimental/ForceNames.scala
@@ -2,7 +2,7 @@
 
 package chisel3.util.experimental
 
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate}
+import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
 import firrtl.Mappers._
 import firrtl._
 import firrtl.annotations._
@@ -49,7 +49,7 @@ object forceName {
     * @param instance Instance to name
     */
   def apply(instance: chisel3.experimental.BaseModule, name: String): Unit = {
-    annotate(new ChiselAnnotation with RunFirrtlTransform  {
+    annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = {
         val t = instance.toAbsoluteTarget
         ForceNameAnnotation(t, name)
@@ -64,7 +64,7 @@ object forceName {
     * @param instance Signal to name
     */
   def apply(instance: chisel3.experimental.BaseModule): Unit = {
-    annotate(new ChiselAnnotation with RunFirrtlTransform  {
+    annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = {
         val t = instance.toAbsoluteTarget
         ForceNameAnnotation(t, instance.instanceName)
@@ -80,8 +80,7 @@ object forceName {
   * @param target signal/instance to force the name
   * @param name name to force it to be
   */
-case class ForceNameAnnotation(target: IsMember, name: String)
-    extends SingleTargetAnnotation[IsMember] {
+case class ForceNameAnnotation(target: IsMember, name: String) extends SingleTargetAnnotation[IsMember] {
   def duplicate(n: IsMember): ForceNameAnnotation = this.copy(target = n, name)
 
   // Errors if renaming to multiple targets
@@ -105,6 +104,7 @@ case class ForceNameAnnotation(target: IsMember, name: String)
   * Could (should?) be moved to FIRRTL.
   */
 private object ForceNamesTransform {
+
   /** Returns the [[IsModule]] which is referred to, or if a [[ReferenceTarget]], the enclosing [[IsModule]]
     *
     * @param a signal/instance/module
@@ -123,10 +123,12 @@ private object ForceNamesTransform {
     */
   def allInstancePaths(graph: InstanceKeyGraph): IsModule => List[List[(Instance, OfModule)]] = {
     val lookup: String => List[List[(Instance, OfModule)]] =
-      str => graph.findInstancesInHierarchy(str)
-        .view
-        .map(_.map(_.toTokens).toList)
-        .toList
+      str =>
+        graph
+          .findInstancesInHierarchy(str)
+          .view
+          .map(_.map(_.toTokens).toList)
+          .toList
     allInstancePaths(lookup) _
   }
 
@@ -136,8 +138,10 @@ private object ForceNamesTransform {
     * @param target target to get all instance paths to
     * @return
     */
-  def allInstancePaths(lookup: String => List[List[(Instance, OfModule)]])
-                      (target: IsModule): List[List[(Instance, OfModule)]] = {
+  def allInstancePaths(
+    lookup: String => List[List[(Instance, OfModule)]]
+  )(target: IsModule
+  ): List[List[(Instance, OfModule)]] = {
     target match {
       case ModuleTarget(circuit, module) =>
         if (circuit == module) List(List((Instance(module), OfModule(module))))
@@ -149,16 +153,13 @@ private object ForceNamesTransform {
     }
   }
 
-
   /** Builds the map of module name to map of old signal/instance name to new signal/instance name
     *
     * @param state CircuitState to operate on
     * @param igraph built instance key graph from state's circuit
     * @return
     */
-  def buildForceNameMap(state: CircuitState,
-                     igraph: => InstanceKeyGraph
-                    ): Option[Map[String, Map[String, String]]] = {
+  def buildForceNameMap(state: CircuitState, igraph: => InstanceKeyGraph): Option[Map[String, Map[String, String]]] = {
     val forceNames = state.annotations.collect { case f: ForceNameAnnotation => f }
     val badNames = mutable.HashSet[ForceNameAnnotation]()
     val allNameMaps = forceNames.groupBy { case f => referringIsModule(f.target) }.mapValues { value =>
@@ -207,9 +208,9 @@ private object ForceNamesTransform {
   *   - Use to avoid prefixing behavior on specific instances whose enclosing modules are inlined
   */
 class ForceNamesTransform extends Transform with DependencyAPIMigration {
-  override def optionalPrerequisites: Seq[TransformDependency] = Seq(Dependency[InlineInstances])
+  override def optionalPrerequisites:  Seq[TransformDependency] = Seq(Dependency[InlineInstances])
   override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
-  override def prerequisites: Seq[TransformDependency] = Seq(Dependency(LowerTypes))
+  override def prerequisites:          Seq[TransformDependency] = Seq(Dependency(LowerTypes))
   override def invalidates(a: Transform): Boolean = firrtl.passes.InferTypes == a
 
   import ForceNamesTransform._
@@ -226,22 +227,23 @@ class ForceNamesTransform extends Transform with DependencyAPIMigration {
     */
   private def forceNamesInModule(
     modToNames: Map[String, Map[String, String]],
-    renameMap: RenameMap,
-    ct: CircuitTarget,
-    igraph: InstanceKeyGraph
-  )(mod: DefModule): DefModule = {
+    renameMap:  RenameMap,
+    ct:         CircuitTarget,
+    igraph:     InstanceKeyGraph
+  )(mod:        DefModule
+  ): DefModule = {
 
     val mt = ct.module(mod.name)
     val instToOfModule = mutable.HashMap[String, String]()
     val names = modToNames.getOrElse(mod.name, Map.empty[String, String])
     // Need to find WRef referring to mems for prefixing
     def onExpr(expr: Expression): Expression = expr match {
-      case ref @ Reference(n, _,_,_) if names.contains(n) =>
+      case ref @ Reference(n, _, _, _) if names.contains(n) =>
         ref.copy(name = names(n))
-      case sub @ SubField(WRef(i, _, _, _), p,_,_) if instToOfModule.contains(i) =>
+      case sub @ SubField(WRef(i, _, _, _), p, _, _) if instToOfModule.contains(i) =>
         val newsub = modToNames.get(instToOfModule(i)) match {
           case Some(map) if map.contains(p) => sub.copy(name = map(p))
-          case _ => sub
+          case _                            => sub
         }
         newsub.map(onExpr)
       case other => other.map(onExpr)
@@ -269,17 +271,19 @@ class ForceNamesTransform extends Transform with DependencyAPIMigration {
       } else port
     }
 
-    val childInstanceHasRename = igraph.getChildInstanceMap(OfModule(mod.name)).exists {
-      o => modToNames.contains(o._2.value)
+    val childInstanceHasRename = igraph.getChildInstanceMap(OfModule(mod.name)).exists { o =>
+      modToNames.contains(o._2.value)
     }
 
-    if(childInstanceHasRename || modToNames.contains(mod.name)) {
+    if (childInstanceHasRename || modToNames.contains(mod.name)) {
       val ns = Namespace(mod)
       val conflicts = names.values.collect { case k if ns.contains(k) => k }
-      if(conflicts.isEmpty) {
+      if (conflicts.isEmpty) {
         mod.map(onPort).map(onStmt)
       } else {
-        throw new FirrtlUserException(s"Cannot force the following names in module ${mod.name} because they conflict: ${conflicts.mkString(",")}")
+        throw new FirrtlUserException(
+          s"Cannot force the following names in module ${mod.name} because they conflict: ${conflicts.mkString(",")}"
+        )
       }
     } else mod
   }
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index 1d5fcb89..fd5c6aa5 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import firrtl.Transform
 import firrtl.passes.{InlineAnnotation, InlineInstances}
-import firrtl.transforms.{NoDedupAnnotation, FlattenAnnotation, Flatten}
+import firrtl.transforms.{Flatten, FlattenAnnotation, NoDedupAnnotation}
 import firrtl.annotations.Annotation
 
 /** Inlines an instance of a module
@@ -40,11 +40,15 @@ import firrtl.annotations.Annotation
   * }}}
   */
 trait InlineInstance { self: BaseModule =>
-  Seq(new ChiselAnnotation with RunFirrtlTransform {
-        def toFirrtl: Annotation = InlineAnnotation(self.toNamed)
-        def transformClass: Class[_ <: Transform] = classOf[InlineInstances] },
-      new ChiselAnnotation {
-        def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed) })
+  Seq(
+    new ChiselAnnotation with RunFirrtlTransform {
+      def toFirrtl:       Annotation = InlineAnnotation(self.toNamed)
+      def transformClass: Class[_ <: Transform] = classOf[InlineInstances]
+    },
+    new ChiselAnnotation {
+      def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed)
+    }
+  )
     .map(chisel3.experimental.annotate(_))
 }
 
@@ -75,10 +79,14 @@ trait InlineInstance { self: BaseModule =>
   * }}}
   */
 trait FlattenInstance { self: BaseModule =>
-  Seq(new ChiselAnnotation with RunFirrtlTransform {
-        def toFirrtl: Annotation = FlattenAnnotation(self.toNamed)
-        def transformClass: Class[_ <: Transform] = classOf[Flatten] },
-      new ChiselAnnotation {
-        def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed) })
-  .map(chisel3.experimental.annotate(_))
+  Seq(
+    new ChiselAnnotation with RunFirrtlTransform {
+      def toFirrtl:       Annotation = FlattenAnnotation(self.toNamed)
+      def transformClass: Class[_ <: Transform] = classOf[Flatten]
+    },
+    new ChiselAnnotation {
+      def toFirrtl: Annotation = NoDedupAnnotation(self.toNamed)
+    }
+  )
+    .map(chisel3.experimental.annotate(_))
 }
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index 93981485..bd46abe9 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -3,7 +3,7 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.experimental.{RunFirrtlTransform, annotate, ChiselAnnotation}
+import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
 import firrtl.annotations._
 import firrtl.ir.{Module => _, _}
 import firrtl.transforms.BlackBoxInlineAnno
@@ -21,11 +21,11 @@ import scala.collection.mutable
 case class ChiselLoadMemoryAnnotation[T <: Data](
   target:      MemBase[T],
   fileName:    String,
-  hexOrBinary: MemoryLoadFileType.FileType = MemoryLoadFileType.Hex
-)
-  extends ChiselAnnotation with RunFirrtlTransform {
+  hexOrBinary: MemoryLoadFileType.FileType = MemoryLoadFileType.Hex)
+    extends ChiselAnnotation
+    with RunFirrtlTransform {
 
-  if(fileName.isEmpty) {
+  if (fileName.isEmpty) {
     throw new Exception(
       s"""LoadMemory from file annotations file empty file name"""
     )
@@ -39,7 +39,6 @@ case class ChiselLoadMemoryAnnotation[T <: Data](
   }
 }
 
-
 /** [[loadMemoryFromFile]] is an annotation generator that helps with loading a memory from a text file as a bind module. This relies on
   * Verilator and Verilog's `\$readmemh` or `\$readmemb`. The [[https://github.com/freechipsproject/treadle Treadle
   * backend]] can also recognize this annotation and load memory at run-time.
@@ -101,22 +100,20 @@ case class ChiselLoadMemoryAnnotation[T <: Data](
   */
 object loadMemoryFromFile {
 
-
   /** Annotate a memory such that it can be initialized using a file
     * @param memory the memory
     * @param filename the file used for initialization
     * @param hexOrBinary whether the file uses a hex or binary number representation
     */
   def apply[T <: Data](
-    memory: MemBase[T],
-    fileName: String,
+    memory:      MemBase[T],
+    fileName:    String,
     hexOrBinary: MemoryLoadFileType.FileType = MemoryLoadFileType.Hex
   ): Unit = {
     annotate(ChiselLoadMemoryAnnotation(memory, fileName, hexOrBinary))
   }
 }
 
-
 /** [[loadMemoryFromFileInline]] is an annotation generator that helps with loading a memory from a text file inlined in
   * the Verilog module. This relies on Verilator and Verilog's `\$readmemh` or `\$readmemb`.
   * The [[https://github.com/freechipsproject/treadle Treadlebackend]] can also recognize this annotation and load memory at run-time.
@@ -179,15 +176,14 @@ object loadMemoryFromFile {
   */
 object loadMemoryFromFileInline {
 
-
   /** Annotate a memory such that it can be initialized inline using a file
     * @param memory the memory
     * @param fileName the file used for initialization
     * @param hexOrBinary whether the file uses a hex or binary number representation
     */
   def apply[T <: Data](
-    memory: MemBase[T],
-    fileName: String,
+    memory:      MemBase[T],
+    fileName:    String,
     hexOrBinary: MemoryLoadFileType.FileType = MemoryLoadFileType.Hex
   ): Unit = {
     annotate(new ChiselAnnotation {
@@ -204,14 +200,14 @@ object loadMemoryFromFileInline {
   * not need this transform to do that.
   */
 class LoadMemoryTransform extends Transform {
-  def inputForm: CircuitForm  = LowForm
+  def inputForm:  CircuitForm = LowForm
   def outputForm: CircuitForm = LowForm
 
   private var memoryCounter: Int = -1
 
   private val bindModules: mutable.ArrayBuffer[BlackBoxInlineAnno] = new mutable.ArrayBuffer()
 
-  private val verilogEmitter:    VerilogEmitter = new VerilogEmitter
+  private val verilogEmitter: VerilogEmitter = new VerilogEmitter
 
   /** run the pass
     * @param circuit the circuit
@@ -219,19 +215,19 @@ class LoadMemoryTransform extends Transform {
     * @return
     */
   def run(circuit: Circuit, annotations: AnnotationSeq): Circuit = {
-    val groups = annotations
-      .collect{ case m: LoadMemoryAnnotation => m }
+    val groups = annotations.collect { case m: LoadMemoryAnnotation => m }
       .groupBy(_.target.serialize)
-    val memoryAnnotations = groups.map { case (key, annos) =>
+    val memoryAnnotations = groups.map {
+      case (key, annos) =>
         if (annos.size > 1) {
           throw new Exception(
             s"Multiple (${annos.size} found for memory $key one LoadMemoryAnnotation is allowed per memory"
           )
         }
         key -> annos.head
-      }
+    }
 
-    val modulesByName = circuit.modules.collect { case module: firrtl.ir.Module =>  module.name -> module }.toMap
+    val modulesByName = circuit.modules.collect { case module: firrtl.ir.Module => module.name -> module }.toMap
 
     /* Walk the module and for memories that are annotated with [[LoadMemoryAnnotation]]s generate the bindable modules for
      * Verilog emission.
@@ -251,32 +247,34 @@ class LoadMemoryTransform extends Transform {
             val writer = new java.io.StringWriter
             val readmem = hexOrBinary match {
               case MemoryLoadFileType.Binary => "$readmemb"
-              case MemoryLoadFileType.Hex => "$readmemh"
+              case MemoryLoadFileType.Hex    => "$readmemh"
             }
 
             modulesByName.get(moduleName.name).foreach { module =>
-                val renderer = verilogEmitter.getRenderer(module, modulesByName)(writer)
-                val loadFileName = lma.getFileName
-
-                memoryCounter += 1
-                val bindsToName = s"BindsTo_${memoryCounter}_${moduleName.name}"
-                renderer.emitVerilogBind(bindsToName,
-                  s"""
-                     |initial begin
-                     |  $readmem("$loadFileName", ${myModule.name}.$componentName);
-                     |end
-                      """.stripMargin)
-                val inLineText = writer.toString + "\n" +
-                  s"""bind ${myModule.name} $bindsToName ${bindsToName}_Inst(.*);"""
-
-                val blackBoxInline = BlackBoxInlineAnno(
-                  moduleName,
-                  moduleName.serialize + "." + componentName + ".v",
-                  inLineText
-                )
-
-                bindModules += blackBoxInline
-              }
+              val renderer = verilogEmitter.getRenderer(module, modulesByName)(writer)
+              val loadFileName = lma.getFileName
+
+              memoryCounter += 1
+              val bindsToName = s"BindsTo_${memoryCounter}_${moduleName.name}"
+              renderer.emitVerilogBind(
+                bindsToName,
+                s"""
+                   |initial begin
+                   |  $readmem("$loadFileName", ${myModule.name}.$componentName);
+                   |end
+                      """.stripMargin
+              )
+              val inLineText = writer.toString + "\n" +
+                s"""bind ${myModule.name} $bindsToName ${bindsToName}_Inst(.*);"""
+
+              val blackBoxInline = BlackBoxInlineAnno(
+                moduleName,
+                moduleName.serialize + "." + componentName + ".v",
+                inLineText
+              )
+
+              bindModules += blackBoxInline
+            }
 
           case _ =>
         }
@@ -284,8 +282,8 @@ class LoadMemoryTransform extends Transform {
 
       def processStatements(statement: Statement): Statement = {
         statement match {
-          case m: DefMemory          => processMemory(m.name)
-          case s                     => s map processStatements
+          case m: DefMemory => processMemory(m.name)
+          case s => s.map(processStatements)
         }
         statement
       }
@@ -299,7 +297,7 @@ class LoadMemoryTransform extends Transform {
       myModule
     }
 
-    circuit map processModule
+    circuit.map(processModule)
   }
 
   def execute(state: CircuitState): CircuitState = {
@@ -309,11 +307,10 @@ class LoadMemoryTransform extends Transform {
       case _ =>
         false
     }
-    if(isVerilog) {
+    if (isVerilog) {
       run(state.circuit, state.annotations)
       state.copy(annotations = state.annotations ++ bindModules)
-    }
-    else {
+    } else {
       state
     }
   }
diff --git a/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala b/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala
index 4dcea99e..de2f207b 100644
--- a/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala
@@ -19,7 +19,7 @@ case object EspressoNotFoundException extends Exception
   */
 object EspressoMinimizer extends Minimizer with LazyLogging {
   def minimize(table: TruthTable): TruthTable =
-    TruthTable.merge(TruthTable.split(table).map{case (table, indexes) => (espresso(table), indexes)})
+    TruthTable.merge(TruthTable.split(table).map { case (table, indexes) => (espresso(table), indexes) })
 
   private def espresso(table: TruthTable): TruthTable = {
     def writeTable(table: TruthTable): String = {
@@ -34,10 +34,9 @@ object EspressoMinimizer extends Minimizer with LazyLogging {
       }
       val tableType: String = defaultType match {
         case '?' => "fr"
-        case _ => "fd"
+        case _   => "fd"
       }
-      val rawTable = table
-        .toString
+      val rawTable = table.toString
         .split("\n")
         .filter(_.contains("->"))
         .mkString("\n")
@@ -69,11 +68,13 @@ object EspressoMinimizer extends Minimizer with LazyLogging {
     logger.trace(s"""espresso input table:
                     |$input
                     |""".stripMargin)
-    val output = try {
-      os.proc("espresso").call(stdin = input).out.chunks.mkString
-    } catch {
-      case e: java.io.IOException if e.getMessage.contains("error=2, No such file or directory") => throw EspressoNotFoundException
-    }
+    val output =
+      try {
+        os.proc("espresso").call(stdin = input).out.chunks.mkString
+      } catch {
+        case e: java.io.IOException if e.getMessage.contains("error=2, No such file or directory") =>
+          throw EspressoNotFoundException
+      }
     logger.trace(s"""espresso output table:
                     |$output
                     |""".stripMargin)
diff --git a/src/main/scala/chisel3/util/experimental/decode/Minimizer.scala b/src/main/scala/chisel3/util/experimental/decode/Minimizer.scala
index 86847710..c4065ac9 100644
--- a/src/main/scala/chisel3/util/experimental/decode/Minimizer.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/Minimizer.scala
@@ -3,6 +3,7 @@
 package chisel3.util.experimental.decode
 
 abstract class Minimizer {
+
   /** Minimize a multi-input multi-output logic function given by the truth table `table`, with function output values
     * on unspecified inputs treated as `default`, and return a minimized PLA-like representation of the function.
     *
@@ -26,4 +27,4 @@ abstract class Minimizer {
     * }}}
     */
   def minimize(table: TruthTable): TruthTable
-}
\ No newline at end of file
+}
diff --git a/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala b/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
index 59120221..a3481869 100644
--- a/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/QMCMinimizer.scala
@@ -125,12 +125,15 @@ object QMCMinimizer extends Minimizer {
     *         b: nonessential prime implicants
     *         c: implicants that are not cover by any of the essential prime implicants
     */
-  private def getEssentialPrimeImplicants(primes: Seq[Implicant], minterms: Seq[Implicant]): (Seq[Implicant], Seq[Implicant], Seq[Implicant]) = {
+  private def getEssentialPrimeImplicants(
+    primes:   Seq[Implicant],
+    minterms: Seq[Implicant]
+  ): (Seq[Implicant], Seq[Implicant], Seq[Implicant]) = {
     // primeCovers(i): implicants that `prime(i)` covers
     val primeCovers = primes.map(p => minterms.filter(p.covers))
     // eliminate prime implicants that can be covered by other prime implicants
-    for (((icover, pi), i) <- (primeCovers zip primes).zipWithIndex) {
-      for (((jcover, pj), _) <- (primeCovers zip primes).zipWithIndex.drop(i + 1)) {
+    for (((icover, pi), i) <- (primeCovers.zip(primes)).zipWithIndex) {
+      for (((jcover, pj), _) <- (primeCovers.zip(primes)).zipWithIndex.drop(i + 1)) {
         // we prefer prime implicants with wider implicants coverage
         if (icover.size > jcover.size && jcover.forall(pi.covers)) {
           // calculate essential prime implicants with `pj` eliminated from prime implicants table
@@ -165,6 +168,7 @@ object QMCMinimizer extends Minimizer {
     * @return Selected nonessential prime implicants
     */
   private def getCover(implicants: Seq[Implicant], minterms: Seq[Implicant]): Seq[Implicant] = {
+
     /** Calculate the implementation cost (using comparators) of a list of implicants, more don't cares is cheaper
       *
       * @param cover Implicant list
@@ -193,7 +197,8 @@ object QMCMinimizer extends Minimizer {
         * @return `a` < `b`
         */
       @tailrec
-      def listLess(a: Seq[Implicant], b: Seq[Implicant]): Boolean = b.nonEmpty && (a.isEmpty || a.head < b.head || a.head == b.head && listLess(a.tail, b.tail))
+      def listLess(a: Seq[Implicant], b: Seq[Implicant]): Boolean =
+        b.nonEmpty && (a.isEmpty || a.head < b.head || a.head == b.head && listLess(a.tail, b.tail))
 
       ca < cb || ca == cb && listLess(a.sortWith(_ < _), b.sortWith(_ < _))
     }
@@ -216,8 +221,14 @@ object QMCMinimizer extends Minimizer {
     // extract decode table to inputs and outputs
     val (inputs, outputs) = table.table.unzip
 
-    require(outputs.map(_.getWidth == table.default.getWidth).reduce(_ && _), "All output BitPats and default BitPat must have the same length")
-    require(if (inputs.toSeq.length > 1) inputs.tail.map(_.width == inputs.head.width).reduce(_ && _) else true, "All input BitPats must have the same length")
+    require(
+      outputs.map(_.getWidth == table.default.getWidth).reduce(_ && _),
+      "All output BitPats and default BitPat must have the same length"
+    )
+    require(
+      if (inputs.toSeq.length > 1) inputs.tail.map(_.width == inputs.head.width).reduce(_ && _) else true,
+      "All input BitPats must have the same length"
+    )
 
     // make sure no two inputs specified in the truth table intersect
     for (t <- inputs.tails; if t.nonEmpty)
@@ -234,9 +245,11 @@ object QMCMinimizer extends Minimizer {
       val outputBp = BitPat("b" + "?" * (m - i - 1) + "1" + "?" * i)
 
       // Minterms, implicants that makes the output to be 1
-      val mint: Seq[Implicant] = table.table.filter { case (_, t) => t.mask.testBit(i) && t.value.testBit(i) }.map(_._1).map(toImplicant)
+      val mint: Seq[Implicant] =
+        table.table.filter { case (_, t) => t.mask.testBit(i) && t.value.testBit(i) }.map(_._1).map(toImplicant)
       // Maxterms, implicants that makes the output to be 0
-      val maxt: Seq[Implicant] = table.table.filter { case (_, t) => t.mask.testBit(i) && !t.value.testBit(i) }.map(_._1).map(toImplicant)
+      val maxt: Seq[Implicant] =
+        table.table.filter { case (_, t) => t.mask.testBit(i) && !t.value.testBit(i) }.map(_._1).map(toImplicant)
       // Don't cares, implicants that can produce either 0 or 1 as output
       val dc: Seq[Implicant] = table.table.filter { case (_, t) => !t.mask.testBit(i) }.map(_._1).map(toImplicant)
 
@@ -251,16 +264,14 @@ object QMCMinimizer extends Minimizer {
 
       implicants.foreach(_.isPrime = true)
       val cols = (0 to n).reverse.map(b => implicants.filter(b == _.bp.mask.bitCount))
-      val mergeTable = cols.map(
-        c => (0 to n).map(
-          b => collection.mutable.Set(c.filter(b == _.bp.value.bitCount):_*)
-        )
-      )
+      val mergeTable = cols.map(c => (0 to n).map(b => collection.mutable.Set(c.filter(b == _.bp.value.bitCount): _*)))
 
       // O(n ^ 3)
       for (i <- 0 to n) {
         for (j <- 0 until n - i) {
-          mergeTable(i)(j).foreach(a => mergeTable(i + 1)(j) ++= mergeTable(i)(j + 1).filter(_ similar a).map(_ merge a))
+          mergeTable(i)(j).foreach(a =>
+            mergeTable(i + 1)(j) ++= mergeTable(i)(j + 1).filter(_.similar(a)).map(_.merge(a))
+          )
         }
         if (defaultToDc) {
           for (j <- 0 until n - i) {
@@ -268,14 +279,14 @@ object QMCMinimizer extends Minimizer {
               if (a.bp.mask.testBit(i) && !a.bp.value.testBit(i)) {
                 // this bit is `0`
                 val t = new BitPat(a.bp.value.setBit(i), a.bp.mask, a.width)
-                if (!maxt.exists(_.intersects(t))) mergeTable(i + 1)(j) += t merge a
+                if (!maxt.exists(_.intersects(t))) mergeTable(i + 1)(j) += t.merge(a)
               }
             }
             for (a <- mergeTable(i)(j + 1).filter(_.isPrime)) {
               if (a.bp.mask.testBit(i) && a.bp.value.testBit(i)) {
                 // this bit is `1`
                 val t = new BitPat(a.bp.value.clearBit(i), a.bp.mask, a.width)
-                if (!maxt.exists(_.intersects(t))) mergeTable(i + 1)(j) += a merge t
+                if (!maxt.exists(_.intersects(t))) mergeTable(i + 1)(j) += a.merge(t)
               }
             }
           }
@@ -288,20 +299,29 @@ object QMCMinimizer extends Minimizer {
       val (essentialPrimeImplicants, nonessentialPrimeImplicants, uncoveredImplicants) =
         getEssentialPrimeImplicants(primeImplicants, implicants)
 
-      (essentialPrimeImplicants ++ getCover(nonessentialPrimeImplicants, uncoveredImplicants)).map(a => (a.bp, outputBp))
+      (essentialPrimeImplicants ++ getCover(nonessentialPrimeImplicants, uncoveredImplicants)).map(a =>
+        (a.bp, outputBp)
+      )
     })
 
-    minimized.tail.foldLeft(table.copy(table = Seq(minimized.head))) { case (tb, t) =>
-      if (tb.table.exists(x => x._1 == t._1)) {
-        tb.copy(table = tb.table.map { case (k, v) =>
-          if (k == t._1) {
-            def ones(bitPat: BitPat) = bitPat.rawString.zipWithIndex.collect{case ('1', x) => x}
-            (k, BitPat("b" + (0 until v.getWidth).map(i => if ((ones(v) ++ ones(t._2)).contains(i)) "1" else "?").mkString))
-          } else (k, v)
-        })
-      } else {
-        tb.copy(table = tb.table :+ t)
-      }
+    minimized.tail.foldLeft(table.copy(table = Seq(minimized.head))) {
+      case (tb, t) =>
+        if (tb.table.exists(x => x._1 == t._1)) {
+          tb.copy(table = tb.table.map {
+            case (k, v) =>
+              if (k == t._1) {
+                def ones(bitPat: BitPat) = bitPat.rawString.zipWithIndex.collect { case ('1', x) => x }
+                (
+                  k,
+                  BitPat(
+                    "b" + (0 until v.getWidth).map(i => if ((ones(v) ++ ones(t._2)).contains(i)) "1" else "?").mkString
+                  )
+                )
+              } else (k, v)
+          })
+        } else {
+          tb.copy(table = tb.table :+ t)
+        }
     }
   }
-}
\ No newline at end of file
+}
diff --git a/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala b/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala
index 322466f9..e742fd66 100644
--- a/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala
@@ -13,10 +13,11 @@ sealed class TruthTable private (val table: Seq[(BitPat, BitPat)], val default:
     def writeRow(map: (BitPat, BitPat)): String =
       s"${map._1.rawString}->${map._2.rawString}"
 
-    (table.map(writeRow) ++ Seq(s"${" "*(inputWidth + 2)}${default.rawString}")).mkString("\n")
+    (table.map(writeRow) ++ Seq(s"${" " * (inputWidth + 2)}${default.rawString}")).mkString("\n")
   }
 
-  def copy(table: Seq[(BitPat, BitPat)] = this.table, default: BitPat = this.default, sort: Boolean = this.sort) = TruthTable(table, default, sort)
+  def copy(table: Seq[(BitPat, BitPat)] = this.table, default: BitPat = this.default, sort: Boolean = this.sort) =
+    TruthTable(table, default, sort)
 
   override def equals(y: Any): Boolean = {
     y match {
@@ -27,27 +28,36 @@ sealed class TruthTable private (val table: Seq[(BitPat, BitPat)], val default:
 }
 
 object TruthTable {
+
   /** Convert a table and default output into a [[TruthTable]]. */
   def apply(table: Iterable[(BitPat, BitPat)], default: BitPat, sort: Boolean = true): TruthTable = {
     require(table.map(_._1.getWidth).toSet.size == 1, "input width not equal.")
     require(table.map(_._2.getWidth).toSet.size == 1, "output width not equal.")
     val outputWidth = table.map(_._2.getWidth).head
-    val mergedTable = table.groupBy(_._1.toString).map { case (key, values) =>
-      // merge same input inputs.
-      values.head._1 -> BitPat(s"b${
-        Seq.tabulate(outputWidth) { i =>
-          val outputSet = values.map(_._2)
-            .map(_.rawString)
-            .map(_ (i))
-            .toSet
-            .filterNot(_ == '?')
-          require(outputSet.size != 2, s"TruthTable conflict in :\n${values.map { case (i, o) => s"${i.rawString}->${o.rawString}" }.mkString("\n")}")
-          outputSet.headOption.getOrElse('?')
-        }.mkString
-      }")
-    }.toSeq
+    val mergedTable = table
+      .groupBy(_._1.toString)
+      .map {
+        case (key, values) =>
+          // merge same input inputs.
+          values.head._1 -> BitPat(s"b${Seq
+            .tabulate(outputWidth) { i =>
+              val outputSet = values
+                .map(_._2)
+                .map(_.rawString)
+                .map(_(i))
+                .toSet
+                .filterNot(_ == '?')
+              require(
+                outputSet.size != 2,
+                s"TruthTable conflict in :\n${values.map { case (i, o) => s"${i.rawString}->${o.rawString}" }.mkString("\n")}"
+              )
+              outputSet.headOption.getOrElse('?')
+            }
+            .mkString}")
+      }
+      .toSeq
     import BitPat.bitPatOrder
-    new TruthTable(if(sort) mergedTable.sorted else mergedTable, default, sort)
+    new TruthTable(if (sort) mergedTable.sorted else mergedTable, default, sort)
   }
 
   /** Parse TruthTable from its string representation. */
@@ -77,10 +87,17 @@ object TruthTable {
       BitPat(s"b${bitPat.rawString.zipWithIndex.filter(b => indexes.contains(b._2)).map(_._1).mkString}")
 
     def tableFilter(indexes: Seq[Int]): Option[(TruthTable, Seq[Int])] = {
-      if(indexes.nonEmpty) Some((TruthTable(
-        table.table.map { case (in, out) => in -> bpFilter(out, indexes) },
-        bpFilter(table.default, indexes)
-      ), indexes)) else None
+      if (indexes.nonEmpty)
+        Some(
+          (
+            TruthTable(
+              table.table.map { case (in, out) => in -> bpFilter(out, indexes) },
+              bpFilter(table.default, indexes)
+            ),
+            indexes
+          )
+        )
+      else None
     }
 
     def index(bitPat: BitPat, bpType: Char): Seq[Int] =
@@ -99,7 +116,12 @@ object TruthTable {
     tables: Seq[(TruthTable, Seq[Int])]
   ): TruthTable = {
     def reIndex(bitPat: BitPat, table: TruthTable, indexes: Seq[Int]): Seq[(Char, Int)] =
-      table.table.map(a => a._1.toString -> a._2).collectFirst{ case (k, v) if k == bitPat.toString => v}.getOrElse(BitPat.dontCare(indexes.size)).rawString.zip(indexes)
+      table.table
+        .map(a => a._1.toString -> a._2)
+        .collectFirst { case (k, v) if k == bitPat.toString => v }
+        .getOrElse(BitPat.dontCare(indexes.size))
+        .rawString
+        .zip(indexes)
     def bitPat(indexedChar: Seq[(Char, Int)]) = BitPat(s"b${indexedChar
       .sortBy(_._2)
       .map(_._1)
diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
index e0bf83b2..4feda672 100644
--- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
@@ -3,13 +3,14 @@
 package chisel3.util.experimental.decode
 
 import chisel3._
-import chisel3.experimental.{ChiselAnnotation, annotate}
-import chisel3.util.{BitPat, pla}
-import chisel3.util.experimental.{BitSet, getAnnotations}
+import chisel3.experimental.{annotate, ChiselAnnotation}
+import chisel3.util.{pla, BitPat}
+import chisel3.util.experimental.{getAnnotations, BitSet}
 import firrtl.annotations.Annotation
 import logger.LazyLogging
 
 object decoder extends LazyLogging {
+
   /** Use a specific [[Minimizer]] to generated decoded signals.
     *
     * @param minimizer  specific [[Minimizer]], can be [[QMCMinimizer]] or [[EspressoMinimizer]].
@@ -71,7 +72,8 @@ object decoder extends LazyLogging {
       qmc(input, truthTable)
     }
 
-    try espresso(input, truthTable) catch {
+    try espresso(input, truthTable)
+    catch {
       case EspressoNotFoundException =>
         logger.error(s"espresso is not found in your PATH:\n${sys.env("PATH").split(":").mkString("\n")}".stripMargin)
         qmcFallBack(input, truthTable)
@@ -81,7 +83,6 @@ object decoder extends LazyLogging {
     }
   }
 
-
   /** Generate a decoder circuit that matches the input to each bitSet.
     *
     * The resulting circuit functions like the following but is optimized with a logic minifier.
@@ -104,9 +105,7 @@ object decoder extends LazyLogging {
         {
           bitSets.zipWithIndex.flatMap {
             case (bs, i) =>
-              bs.terms.map(bp =>
-                s"${bp.rawString}->${if (errorBit) "0"}${"0" * (bitSets.size - i - 1)}1${"0" * i}"
-              )
+              bs.terms.map(bp => s"${bp.rawString}->${if (errorBit) "0"}${"0" * (bitSets.size - i - 1)}1${"0" * i}")
           } ++ Seq(s"${if (errorBit) "1"}${"?" * bitSets.size}")
         }.mkString("\n")
       )
diff --git a/src/main/scala/chisel3/util/experimental/getAnnotations.scala b/src/main/scala/chisel3/util/experimental/getAnnotations.scala
index dc9b75ee..ac6e6bd1 100644
--- a/src/main/scala/chisel3/util/experimental/getAnnotations.scala
+++ b/src/main/scala/chisel3/util/experimental/getAnnotations.scala
@@ -4,6 +4,7 @@ import chisel3.internal.Builder
 import firrtl.AnnotationSeq
 
 object getAnnotations {
+
   /** Returns the global Annotations */
   def apply(): AnnotationSeq = Builder.annotationSeq
 }
diff --git a/src/main/scala/chisel3/util/experimental/group.scala b/src/main/scala/chisel3/util/experimental/group.scala
index e43115d0..202c95d8 100644
--- a/src/main/scala/chisel3/util/experimental/group.scala
+++ b/src/main/scala/chisel3/util/experimental/group.scala
@@ -3,7 +3,7 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate}
+import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.internal.requireIsHardware
 import firrtl.Transform
 import firrtl.transforms.{GroupAnnotation, GroupComponents}
@@ -46,12 +46,14 @@ object group {
     * @tparam T Parent type of input components
     */
   def apply[T <: Data](
-      components: Seq[T],
-      newModule: String,
-      newInstance: String,
-      outputSuffix: Option[String] = None,
-      inputSuffix: Option[String] = None
-  )(implicit compileOptions: CompileOptions): Unit = {
+    components:   Seq[T],
+    newModule:    String,
+    newInstance:  String,
+    outputSuffix: Option[String] = None,
+    inputSuffix:  Option[String] = None
+  )(
+    implicit compileOptions: CompileOptions
+  ): Unit = {
     if (compileOptions.checkSynthesizable) {
       components.foreach { data =>
         requireIsHardware(data, s"Component ${data.toString} is marked to group, but is not bound.")
@@ -64,4 +66,3 @@ object group {
     })
   }
 }
-
diff --git a/src/main/scala/chisel3/util/pla.scala b/src/main/scala/chisel3/util/pla.scala
index c57ca962..d4707d26 100644
--- a/src/main/scala/chisel3/util/pla.scala
+++ b/src/main/scala/chisel3/util/pla.scala
@@ -68,7 +68,8 @@ object pla {
 
     val inverterMask = invert.value & invert.mask
     if (inverterMask.bitCount != 0)
-      require(invert.getWidth == numberOfOutputs,
+      require(
+        invert.getWidth == numberOfOutputs,
         "non-zero inverter mask must have the same width as the output part of specified PLA table"
       )
 
@@ -99,28 +100,28 @@ object pla {
 
     // the OR matrix
     val orMatrixOutputs: UInt = Cat(
-        Seq
-          .tabulate(numberOfOutputs) { i =>
-            val andMatrixLines = table
-              // OR matrix composed by input terms which makes this output bit a `1`
-              .filter {
-                case (_, or) => or.mask.testBit(i) && or.value.testBit(i)
-              }.map {
-                case (inputTerm, _) =>
-                  andMatrixOutputs(inputTerm.toString)
-              }
-            if (andMatrixLines.isEmpty) false.B
-            else Cat(andMatrixLines).orR()
-          }
-          .reverse
-      )
+      Seq
+        .tabulate(numberOfOutputs) { i =>
+          val andMatrixLines = table
+            // OR matrix composed by input terms which makes this output bit a `1`
+            .filter {
+              case (_, or) => or.mask.testBit(i) && or.value.testBit(i)
+            }.map {
+              case (inputTerm, _) =>
+                andMatrixOutputs(inputTerm.toString)
+            }
+          if (andMatrixLines.isEmpty) false.B
+          else Cat(andMatrixLines).orR()
+        }
+        .reverse
+    )
 
     // the INV matrix, useful for decoders
     val invMatrixOutputs: UInt = Cat(
       Seq
         .tabulate(numberOfOutputs) { i =>
           if (inverterMask.testBit(i)) ~orMatrixOutputs(i)
-          else                          orMatrixOutputs(i)
+          else orMatrixOutputs(i)
         }
         .reverse
     )
diff --git a/src/main/scala/chisel3/util/random/FibonacciLFSR.scala b/src/main/scala/chisel3/util/random/FibonacciLFSR.scala
index 32f5caa8..4da51a4e 100644
--- a/src/main/scala/chisel3/util/random/FibonacciLFSR.scala
+++ b/src/main/scala/chisel3/util/random/FibonacciLFSR.scala
@@ -40,14 +40,16 @@ import chisel3._
   * $paramUpdateSeed
   */
 class FibonacciLFSR(
-  width: Int,
-  taps: Set[Int],
-  seed: Option[BigInt] = Some(1),
+  width:         Int,
+  taps:          Set[Int],
+  seed:          Option[BigInt] = Some(1),
   val reduction: LFSRReduce = XOR,
-  step: Int = 1,
-  updateSeed: Boolean = false) extends PRNG(width, seed, step, updateSeed) with LFSR {
+  step:          Int = 1,
+  updateSeed:    Boolean = false)
+    extends PRNG(width, seed, step, updateSeed)
+    with LFSR {
 
-  def delta(s: Seq[Bool]): Seq[Bool] = taps.map{ case i => s(i - 1) }.reduce(reduction) +: s.dropRight(1)
+  def delta(s: Seq[Bool]): Seq[Bool] = taps.map { case i => s(i - 1) }.reduce(reduction) +: s.dropRight(1)
 
 }
 
@@ -87,11 +89,12 @@ object FibonacciLFSR {
     * $paramReduction
     */
   def apply(
-    width: Int,
-    taps: Set[Int],
+    width:     Int,
+    taps:      Set[Int],
     increment: Bool = true.B,
-    seed: Option[BigInt] = Some(1),
-    reduction: LFSRReduce = XOR): UInt = PRNG(new FibonacciLFSR(width, taps, seed, reduction), increment)
+    seed:      Option[BigInt] = Some(1),
+    reduction: LFSRReduce = XOR
+  ): UInt = PRNG(new FibonacciLFSR(width, taps, seed, reduction), increment)
 
   /** Return a pseudorandom [[UInt]] generated using a maximal period [[FibonacciLFSR]]
     * $paramWidth
@@ -100,9 +103,10 @@ object FibonacciLFSR {
     * $paramReduction
     */
   def maxPeriod(
-    width: Int,
+    width:     Int,
     increment: Bool = true.B,
-    seed: Option[BigInt] = Some(1),
-    reduction: LFSRReduce = XOR): UInt = PRNG(new MaxPeriodFibonacciLFSR(width, seed, reduction), increment)
+    seed:      Option[BigInt] = Some(1),
+    reduction: LFSRReduce = XOR
+  ): UInt = PRNG(new MaxPeriodFibonacciLFSR(width, seed, reduction), increment)
 
 }
diff --git a/src/main/scala/chisel3/util/random/GaloisLFSR.scala b/src/main/scala/chisel3/util/random/GaloisLFSR.scala
index 68346e82..f452cf75 100644
--- a/src/main/scala/chisel3/util/random/GaloisLFSR.scala
+++ b/src/main/scala/chisel3/util/random/GaloisLFSR.scala
@@ -38,21 +38,21 @@ import chisel3._
   * $paramUpdateSeed
   */
 class GaloisLFSR(
-  width: Int,
-  taps: Set[Int],
-  seed: Option[BigInt] = Some(1),
+  width:         Int,
+  taps:          Set[Int],
+  seed:          Option[BigInt] = Some(1),
   val reduction: LFSRReduce = XOR,
-  step: Int = 1,
-  updateSeed: Boolean = false) extends PRNG(width, seed, step, updateSeed) with LFSR {
+  step:          Int = 1,
+  updateSeed:    Boolean = false)
+    extends PRNG(width, seed, step, updateSeed)
+    with LFSR {
 
   def delta(s: Seq[Bool]): Seq[Bool] = {
     val first = s.head
-    (s.tail :+ first)
-      .zipWithIndex
-      .map {
-        case (a, i) if taps(i + 1) && (i + 1 != s.size) => reduction(a, first)
-        case (a, _)                                     => a
-      }
+    (s.tail :+ first).zipWithIndex.map {
+      case (a, i) if taps(i + 1) && (i + 1 != s.size) => reduction(a, first)
+      case (a, _)                                     => a
+    }
   }
 
 }
@@ -93,11 +93,12 @@ object GaloisLFSR {
     * $paramReduction
     */
   def apply(
-    width: Int,
-    taps: Set[Int],
+    width:     Int,
+    taps:      Set[Int],
     increment: Bool = true.B,
-    seed: Option[BigInt] = Some(1),
-    reduction: LFSRReduce = XOR): UInt = PRNG(new GaloisLFSR(width, taps, seed, reduction), increment)
+    seed:      Option[BigInt] = Some(1),
+    reduction: LFSRReduce = XOR
+  ): UInt = PRNG(new GaloisLFSR(width, taps, seed, reduction), increment)
 
   /** Return a pseudorandom [[UInt]] generated using a maximal period [[GaloisLFSR]]
     * $paramWidth
@@ -106,9 +107,10 @@ object GaloisLFSR {
     * $paramReduction
     */
   def maxPeriod(
-    width: Int,
+    width:     Int,
     increment: Bool = true.B,
-    seed: Option[BigInt] = Some(1),
-    reduction: LFSRReduce = XOR): UInt = PRNG(new MaxPeriodGaloisLFSR(width, seed, reduction), increment)
+    seed:      Option[BigInt] = Some(1),
+    reduction: LFSRReduce = XOR
+  ): UInt = PRNG(new MaxPeriodGaloisLFSR(width, seed, reduction), increment)
 
 }
diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala
index 08b124f6..b26cfa5d 100644
--- a/src/main/scala/chisel3/util/random/LFSR.scala
+++ b/src/main/scala/chisel3/util/random/LFSR.scala
@@ -48,7 +48,8 @@ trait LFSR extends PRNG {
   def reduction: LFSRReduce
 
   override protected def resetValue: Vec[Bool] = seed match {
-    case Some(s) => reduction match {
+    case Some(s) =>
+      reduction match {
         case XOR  => require(s != 0, "Seed cannot be zero")
         case XNOR => require(s != BigInt(2).pow(width) - 1, "Seed cannot be all ones (max value)")
       }
@@ -87,8 +88,9 @@ object LFSR {
     FibonacciLFSR.maxPeriod(width, increment, seed, XOR)
 
   /** Utility used to report an unknown tap width */
-  private [random] def badWidth(width: Int): Nothing = throw new IllegalArgumentException(
-    s"No max period LFSR taps stored for requested width '$width'")
+  private[random] def badWidth(width: Int): Nothing = throw new IllegalArgumentException(
+    s"No max period LFSR taps stored for requested width '$width'"
+  )
 
   /** A mapping of widths to a sequence of known LFSR taps that produce a maximal period LFSR. These work for either a
     * [[chisel3.util.random.FibonacciLFSR Fibonacci LFSR]] or a [[chisel3.util.random.GaloisLFSR Galois LFSR]]. Taps are
@@ -104,796 +106,798 @@ object LFSR {
 
   /** First portion of known taps (a combined map hits the 64KB JVM method limit) */
   private def tapsFirst = Map(
-    2    -> Seq(Set(2, 1)),
-    3    -> Seq(Set(3, 2)),
-    4    -> Seq(Set(4, 3)),
-    5    -> Seq(Set(5, 3), Set(5, 4, 3, 2)),
-    6    -> Seq(Set(6, 5), Set(6, 5, 3, 2)),
-    7    -> Seq(Set(7, 6), Set(7, 6, 5, 4)),
-    8    -> Seq(Set(8, 6, 5, 4)),
-    9    -> Seq(Set(9, 5), Set(9, 8, 6, 5)),
-    10   -> Seq(Set(10, 7), Set(10, 9, 7, 6)),
-    11   -> Seq(Set(11, 9), Set(11, 10, 9, 7)),
-    12   -> Seq(Set(12, 11, 8, 6)),
-    13   -> Seq(Set(13, 12, 10, 9)),
-    14   -> Seq(Set(14, 13, 11, 9)),
-    15   -> Seq(Set(15, 14), Set(15, 14, 13, 11)),
-    16   -> Seq(Set(16, 14, 13, 11)),
-    17   -> Seq(Set(17, 14), Set(17, 16, 15, 14)),
-    18   -> Seq(Set(18, 11), Set(18, 17, 16, 13)),
-    19   -> Seq(Set(19, 18, 17, 14)),
-    20   -> Seq(Set(20, 17), Set(20, 19, 16, 14)),
-    21   -> Seq(Set(21, 19), Set(21, 20, 19, 16)),
-    22   -> Seq(Set(22, 21), Set(22, 19, 18, 17)),
-    23   -> Seq(Set(23, 18), Set(23, 22, 20, 18)),
-    24   -> Seq(Set(24, 23, 21, 20)),
-    25   -> Seq(Set(25, 22), Set(25, 24, 23, 22)),
-    26   -> Seq(Set(26, 25, 24, 20)),
-    27   -> Seq(Set(27, 26, 25, 22)),
-    28   -> Seq(Set(28, 25), Set(28, 27, 24, 22)),
-    29   -> Seq(Set(29, 27), Set(29, 28, 27, 25)),
-    30   -> Seq(Set(30, 29, 26, 24)),
-    31   -> Seq(Set(31, 28), Set(31, 30, 29, 28)),
-    32   -> Seq(Set(32, 30, 26, 25)),
-    33   -> Seq(Set(33, 20), Set(33, 32, 29, 27)),
-    34   -> Seq(Set(34, 31, 30, 26)),
-    35   -> Seq(Set(35, 33), Set(35, 34, 28, 27)),
-    36   -> Seq(Set(36, 25), Set(36, 35, 29, 28)),
-    37   -> Seq(Set(37, 36, 33, 31)),
-    38   -> Seq(Set(38, 37, 33, 32)),
-    39   -> Seq(Set(39, 35), Set(39, 38, 35, 32)),
-    40   -> Seq(Set(40, 37, 36, 35)),
-    41   -> Seq(Set(41, 38), Set(41, 40, 39, 38)),
-    42   -> Seq(Set(42, 40, 37, 35)),
-    43   -> Seq(Set(43, 42, 38, 37)),
-    44   -> Seq(Set(44, 42, 39, 38)),
-    45   -> Seq(Set(45, 44, 42, 41)),
-    46   -> Seq(Set(46, 40, 39, 38)),
-    47   -> Seq(Set(47, 42), Set(47, 46, 43, 42)),
-    48   -> Seq(Set(48, 44, 41, 39)),
-    49   -> Seq(Set(49, 40), Set(49, 45, 44, 43)),
-    50   -> Seq(Set(50, 48, 47, 46)),
-    51   -> Seq(Set(51, 50, 48, 45)),
-    52   -> Seq(Set(52, 49), Set(52, 51, 49, 46)),
-    53   -> Seq(Set(53, 52, 51, 47)),
-    54   -> Seq(Set(54, 51, 48, 46)),
-    55   -> Seq(Set(55, 31), Set(55, 54, 53, 49)),
-    56   -> Seq(Set(56, 54, 52, 49)),
-    57   -> Seq(Set(57, 50), Set(57, 55, 54, 52)),
-    58   -> Seq(Set(58, 39), Set(58, 57, 53, 52)),
-    59   -> Seq(Set(59, 57, 55, 52)),
-    60   -> Seq(Set(60, 59), Set(60, 58, 56, 55)),
-    61   -> Seq(Set(61, 60, 59, 56)),
-    62   -> Seq(Set(62, 59, 57, 56)),
-    63   -> Seq(Set(63, 62), Set(63, 62, 59, 58)),
-    64   -> Seq(Set(64, 63, 61, 60)),
-    65   -> Seq(Set(65, 47), Set(65, 64, 62, 61)),
-    66   -> Seq(Set(66, 60, 58, 57)),
-    67   -> Seq(Set(67, 66, 65, 62)),
-    68   -> Seq(Set(68, 59), Set(68, 67, 63, 61)),
-    69   -> Seq(Set(69, 67, 64, 63)),
-    70   -> Seq(Set(70, 69, 67, 65)),
-    71   -> Seq(Set(71, 65), Set(71, 70, 68, 66)),
-    72   -> Seq(Set(72, 69, 63, 62)),
-    73   -> Seq(Set(73, 48), Set(73, 71, 70, 69)),
-    74   -> Seq(Set(74, 71, 70, 67)),
-    75   -> Seq(Set(75, 74, 72, 69)),
-    76   -> Seq(Set(76, 74, 72, 71)),
-    77   -> Seq(Set(77, 75, 72, 71)),
-    78   -> Seq(Set(78, 77, 76, 71)),
-    79   -> Seq(Set(79, 70), Set(79, 77, 76, 75)),
-    80   -> Seq(Set(80, 78, 76, 71)),
-    81   -> Seq(Set(81, 77), Set(81, 79, 78, 75)),
-    82   -> Seq(Set(82, 78, 76, 73)),
-    83   -> Seq(Set(83, 81, 79, 76)),
-    84   -> Seq(Set(84, 71), Set(84, 83, 77, 75)),
-    85   -> Seq(Set(85, 84, 83, 77)),
-    86   -> Seq(Set(86, 84, 81, 80)),
-    87   -> Seq(Set(87, 74), Set(87, 86, 82, 80)),
-    88   -> Seq(Set(88, 80, 79, 77)),
-    89   -> Seq(Set(89, 51), Set(89, 86, 84, 83)),
-    90   -> Seq(Set(90, 88, 87, 85)),
-    91   -> Seq(Set(91, 90, 86, 83)),
-    92   -> Seq(Set(92, 90, 87, 86)),
-    93   -> Seq(Set(93, 91), Set(93, 91, 90, 87)),
-    94   -> Seq(Set(94, 73), Set(94, 93, 89, 88)),
-    95   -> Seq(Set(95, 84), Set(95, 94, 90, 88)),
-    96   -> Seq(Set(96, 90, 87, 86)),
-    97   -> Seq(Set(97, 91), Set(97, 95, 93, 91)),
-    98   -> Seq(Set(98, 87), Set(98, 97, 91, 90)),
-    99   -> Seq(Set(99, 95, 94, 92)),
-    100  -> Seq(Set(100, 63), Set(100, 98, 93, 92)),
-    101  -> Seq(Set(101, 100, 95, 94)),
-    102  -> Seq(Set(102, 99, 97, 96)),
-    103  -> Seq(Set(103, 94), Set(103, 102, 99, 94)),
-    104  -> Seq(Set(104, 103, 94, 93)),
-    105  -> Seq(Set(105, 89), Set(105, 104, 99, 98)),
-    106  -> Seq(Set(106, 91), Set(106, 105, 101, 100)),
-    107  -> Seq(Set(107, 105, 99, 98)),
-    108  -> Seq(Set(108, 77), Set(108, 103, 97, 96)),
-    109  -> Seq(Set(109, 107, 105, 104)),
-    110  -> Seq(Set(110, 109, 106, 104)),
-    111  -> Seq(Set(111, 101), Set(111, 109, 107, 104)),
-    112  -> Seq(Set(112, 108, 106, 101)),
-    113  -> Seq(Set(113, 104), Set(113, 111, 110, 108)),
-    114  -> Seq(Set(114, 113, 112, 103)),
-    115  -> Seq(Set(115, 110, 108, 107)),
-    116  -> Seq(Set(116, 114, 111, 110)),
-    117  -> Seq(Set(117, 116, 115, 112)),
-    118  -> Seq(Set(118, 85), Set(118, 116, 113, 112)),
-    119  -> Seq(Set(119, 111), Set(119, 116, 111, 110)),
-    120  -> Seq(Set(120, 118, 114, 111)),
-    121  -> Seq(Set(121, 103), Set(121, 120, 116, 113)),
-    122  -> Seq(Set(122, 121, 120, 116)),
-    123  -> Seq(Set(123, 121), Set(123, 122, 119, 115)),
-    124  -> Seq(Set(124, 87), Set(124, 119, 118, 117)),
-    125  -> Seq(Set(125, 120, 119, 118)),
-    126  -> Seq(Set(126, 124, 122, 119)),
-    127  -> Seq(Set(127, 126), Set(127, 126, 124, 120)),
-    128  -> Seq(Set(128, 127, 126, 121)),
-    129  -> Seq(Set(129, 124), Set(129, 128, 125, 124)),
-    130  -> Seq(Set(130, 127), Set(130, 129, 128, 125)),
-    131  -> Seq(Set(131, 129, 128, 123)),
-    132  -> Seq(Set(132, 103), Set(132, 130, 127, 123)),
-    133  -> Seq(Set(133, 131, 125, 124)),
-    134  -> Seq(Set(134, 77), Set(134, 133, 129, 127)),
-    135  -> Seq(Set(135, 124), Set(135, 132, 131, 129)),
-    136  -> Seq(Set(136, 134, 133, 128)),
-    137  -> Seq(Set(137, 116), Set(137, 136, 133, 126)),
-    138  -> Seq(Set(138, 137, 131, 130)),
-    139  -> Seq(Set(139, 136, 134, 131)),
-    140  -> Seq(Set(140, 111), Set(140, 139, 136, 132)),
-    141  -> Seq(Set(141, 140, 135, 128)),
-    142  -> Seq(Set(142, 121), Set(142, 141, 139, 132)),
-    143  -> Seq(Set(143, 141, 140, 138)),
-    144  -> Seq(Set(144, 142, 140, 137)),
-    145  -> Seq(Set(145, 93), Set(145, 144, 140, 139)),
-    146  -> Seq(Set(146, 144, 143, 141)),
-    147  -> Seq(Set(147, 145, 143, 136)),
-    148  -> Seq(Set(148, 121), Set(148, 145, 143, 141)),
-    149  -> Seq(Set(149, 142, 140, 139)),
-    150  -> Seq(Set(150, 97), Set(150, 148, 147, 142)),
-    151  -> Seq(Set(151, 148), Set(151, 150, 149, 148)),
-    152  -> Seq(Set(152, 150, 149, 146)),
-    153  -> Seq(Set(153, 152), Set(153, 149, 148, 145)),
-    154  -> Seq(Set(154, 153, 149, 145)),
-    155  -> Seq(Set(155, 151, 150, 148)),
-    156  -> Seq(Set(156, 153, 151, 147)),
-    157  -> Seq(Set(157, 155, 152, 151)),
-    158  -> Seq(Set(158, 153, 152, 150)),
-    159  -> Seq(Set(159, 128), Set(159, 156, 153, 148)),
-    160  -> Seq(Set(160, 158, 157, 155)),
-    161  -> Seq(Set(161, 143), Set(161, 159, 158, 155)),
-    162  -> Seq(Set(162, 158, 155, 154)),
-    163  -> Seq(Set(163, 160, 157, 156)),
-    164  -> Seq(Set(164, 159, 158, 152)),
-    165  -> Seq(Set(165, 162, 157, 156)),
-    166  -> Seq(Set(166, 164, 163, 156)),
-    167  -> Seq(Set(167, 161), Set(167, 165, 163, 161)),
-    168  -> Seq(Set(168, 162, 159, 152)),
-    169  -> Seq(Set(169, 135), Set(169, 164, 163, 161)),
-    170  -> Seq(Set(170, 147), Set(170, 169, 166, 161)),
-    171  -> Seq(Set(171, 169, 166, 165)),
-    172  -> Seq(Set(172, 165), Set(172, 169, 165, 161)),
-    173  -> Seq(Set(173, 171, 168, 165)),
-    174  -> Seq(Set(174, 161), Set(174, 169, 166, 165)),
-    175  -> Seq(Set(175, 169), Set(175, 173, 171, 169)),
-    176  -> Seq(Set(176, 167, 165, 164)),
-    177  -> Seq(Set(177, 169), Set(177, 175, 174, 172)),
-    178  -> Seq(Set(178, 91), Set(178, 176, 171, 170)),
-    179  -> Seq(Set(179, 178, 177, 175)),
-    180  -> Seq(Set(180, 173, 170, 168)),
-    181  -> Seq(Set(181, 180, 175, 174)),
-    182  -> Seq(Set(182, 181, 176, 174)),
-    183  -> Seq(Set(183, 127), Set(183, 179, 176, 175)),
-    184  -> Seq(Set(184, 177, 176, 175)),
-    185  -> Seq(Set(185, 161), Set(185, 184, 182, 177)),
-    186  -> Seq(Set(186, 180, 178, 177)),
-    187  -> Seq(Set(187, 182, 181, 180)),
-    188  -> Seq(Set(188, 186, 183, 182)),
-    189  -> Seq(Set(189, 187, 184, 183)),
-    190  -> Seq(Set(190, 188, 184, 177)),
-    191  -> Seq(Set(191, 182), Set(191, 187, 185, 184)),
-    192  -> Seq(Set(192, 190, 178, 177)),
-    193  -> Seq(Set(193, 178), Set(193, 189, 186, 184)),
-    194  -> Seq(Set(194, 107), Set(194, 192, 191, 190)),
-    195  -> Seq(Set(195, 193, 192, 187)),
-    196  -> Seq(Set(196, 194, 187, 185)),
-    197  -> Seq(Set(197, 195, 193, 188)),
-    198  -> Seq(Set(198, 133), Set(198, 193, 190, 183)),
-    199  -> Seq(Set(199, 165), Set(199, 198, 195, 190)),
-    200  -> Seq(Set(200, 198, 197, 195)),
-    201  -> Seq(Set(201, 187), Set(201, 199, 198, 195)),
-    202  -> Seq(Set(202, 147), Set(202, 198, 196, 195)),
-    203  -> Seq(Set(203, 202, 196, 195)),
-    204  -> Seq(Set(204, 201, 200, 194)),
-    205  -> Seq(Set(205, 203, 200, 196)),
-    206  -> Seq(Set(206, 201, 197, 196)),
-    207  -> Seq(Set(207, 164), Set(207, 206, 201, 198)),
-    208  -> Seq(Set(208, 207, 205, 199)),
-    209  -> Seq(Set(209, 203), Set(209, 207, 206, 204)),
-    210  -> Seq(Set(210, 207, 206, 198)),
-    211  -> Seq(Set(211, 203, 201, 200)),
-    212  -> Seq(Set(212, 107), Set(212, 209, 208, 205)),
-    213  -> Seq(Set(213, 211, 208, 207)),
-    214  -> Seq(Set(214, 213, 211, 209)),
-    215  -> Seq(Set(215, 192), Set(215, 212, 210, 209)),
-    216  -> Seq(Set(216, 215, 213, 209)),
-    217  -> Seq(Set(217, 172), Set(217, 213, 212, 211)),
-    218  -> Seq(Set(218, 207), Set(218, 217, 211, 210)),
-    219  -> Seq(Set(219, 218, 215, 211)),
-    220  -> Seq(Set(220, 211, 210, 208)),
-    221  -> Seq(Set(221, 219, 215, 213)),
-    222  -> Seq(Set(222, 220, 217, 214)),
-    223  -> Seq(Set(223, 190), Set(223, 221, 219, 218)),
-    224  -> Seq(Set(224, 222, 217, 212)),
-    225  -> Seq(Set(225, 193), Set(225, 224, 220, 215)),
-    226  -> Seq(Set(226, 223, 219, 216)),
-    227  -> Seq(Set(227, 223, 218, 217)),
-    228  -> Seq(Set(228, 226, 217, 216)),
-    229  -> Seq(Set(229, 228, 225, 219)),
-    230  -> Seq(Set(230, 224, 223, 222)),
-    231  -> Seq(Set(231, 205), Set(231, 229, 227, 224)),
-    232  -> Seq(Set(232, 228, 223, 221)),
-    233  -> Seq(Set(233, 159), Set(233, 232, 229, 224)),
-    234  -> Seq(Set(234, 203), Set(234, 232, 225, 223)),
-    235  -> Seq(Set(235, 234, 229, 226)),
-    236  -> Seq(Set(236, 231), Set(236, 229, 228, 226)),
-    237  -> Seq(Set(237, 236, 233, 230)),
-    238  -> Seq(Set(238, 237, 236, 233)),
-    239  -> Seq(Set(239, 203), Set(239, 238, 232, 227)),
-    240  -> Seq(Set(240, 237, 235, 232)),
-    241  -> Seq(Set(241, 171), Set(241, 237, 233, 232)),
-    242  -> Seq(Set(242, 241, 236, 231)),
-    243  -> Seq(Set(243, 242, 238, 235)),
-    244  -> Seq(Set(244, 243, 240, 235)),
-    245  -> Seq(Set(245, 244, 241, 239)),
-    246  -> Seq(Set(246, 245, 244, 235)),
-    247  -> Seq(Set(247, 165), Set(247, 245, 243, 238)),
-    248  -> Seq(Set(248, 238, 234, 233)),
-    249  -> Seq(Set(249, 163), Set(249, 248, 245, 242)),
-    250  -> Seq(Set(250, 147), Set(250, 247, 245, 240)),
-    251  -> Seq(Set(251, 249, 247, 244)),
-    252  -> Seq(Set(252, 185), Set(252, 251, 247, 241)),
-    253  -> Seq(Set(253, 252, 247, 246)),
-    254  -> Seq(Set(254, 253, 252, 247)),
-    255  -> Seq(Set(255, 203), Set(255, 253, 252, 250)),
-    256  -> Seq(Set(256, 254, 251, 246)),
-    257  -> Seq(Set(257, 245), Set(257, 255, 251, 250)),
-    258  -> Seq(Set(258, 175), Set(258, 254, 252, 249)),
-    259  -> Seq(Set(259, 257, 253, 249)),
-    260  -> Seq(Set(260, 253, 252, 250)),
-    261  -> Seq(Set(261, 257, 255, 254)),
-    262  -> Seq(Set(262, 258, 254, 253)),
-    263  -> Seq(Set(263, 170), Set(263, 261, 258, 252)),
-    264  -> Seq(Set(264, 263, 255, 254)),
-    265  -> Seq(Set(265, 223), Set(265, 263, 262, 260)),
-    266  -> Seq(Set(266, 219), Set(266, 265, 260, 259)),
-    267  -> Seq(Set(267, 264, 261, 259)),
-    268  -> Seq(Set(268, 243), Set(268, 267, 264, 258)),
-    269  -> Seq(Set(269, 268, 263, 262)),
-    270  -> Seq(Set(270, 217), Set(270, 267, 263, 260)),
-    271  -> Seq(Set(271, 213), Set(271, 265, 264, 260)),
-    272  -> Seq(Set(272, 270, 266, 263)),
-    273  -> Seq(Set(273, 250), Set(273, 272, 271, 266)),
-    274  -> Seq(Set(274, 207), Set(274, 272, 267, 265)),
-    275  -> Seq(Set(275, 266, 265, 264)),
-    276  -> Seq(Set(276, 275, 273, 270)),
-    277  -> Seq(Set(277, 274, 271, 265)),
-    278  -> Seq(Set(278, 273), Set(278, 277, 274, 273)),
-    279  -> Seq(Set(279, 274), Set(279, 278, 275, 274)),
-    280  -> Seq(Set(280, 278, 275, 271)),
-    281  -> Seq(Set(281, 188), Set(281, 280, 277, 272)),
-    282  -> Seq(Set(282, 247), Set(282, 278, 277, 272)),
-    283  -> Seq(Set(283, 278, 276, 271)),
-    284  -> Seq(Set(284, 165), Set(284, 279, 278, 276)),
-    285  -> Seq(Set(285, 280, 278, 275)),
-    286  -> Seq(Set(286, 217), Set(286, 285, 276, 271)),
-    287  -> Seq(Set(287, 216), Set(287, 285, 282, 281)),
-    288  -> Seq(Set(288, 287, 278, 277)),
-    289  -> Seq(Set(289, 268), Set(289, 286, 285, 277)),
-    290  -> Seq(Set(290, 288, 287, 285)),
-    291  -> Seq(Set(291, 286, 280, 279)),
-    292  -> Seq(Set(292, 195), Set(292, 291, 289, 285)),
-    293  -> Seq(Set(293, 292, 287, 282)),
-    294  -> Seq(Set(294, 233), Set(294, 292, 291, 285)),
-    295  -> Seq(Set(295, 247), Set(295, 293, 291, 290)),
-    296  -> Seq(Set(296, 292, 287, 285)),
-    297  -> Seq(Set(297, 292), Set(297, 296, 293, 292)),
-    298  -> Seq(Set(298, 294, 290, 287)),
-    299  -> Seq(Set(299, 295, 293, 288)),
-    300  -> Seq(Set(300, 293), Set(300, 290, 288, 287)),
-    301  -> Seq(Set(301, 299, 296, 292)),
-    302  -> Seq(Set(302, 261), Set(302, 297, 293, 290)),
-    303  -> Seq(Set(303, 297, 291, 290)),
-    304  -> Seq(Set(304, 303, 302, 293)),
-    305  -> Seq(Set(305, 203), Set(305, 303, 299, 298)),
-    306  -> Seq(Set(306, 305, 303, 299)),
-    307  -> Seq(Set(307, 305, 303, 299)),
-    308  -> Seq(Set(308, 306, 299, 293)),
-    309  -> Seq(Set(309, 307, 302, 299)),
-    310  -> Seq(Set(310, 309, 305, 302)),
-    311  -> Seq(Set(311, 308, 306, 304)),
-    312  -> Seq(Set(312, 307, 302, 301)),
-    313  -> Seq(Set(313, 234), Set(313, 312, 310, 306)),
-    314  -> Seq(Set(314, 299), Set(314, 311, 305, 300)),
-    315  -> Seq(Set(315, 314, 306, 305)),
-    316  -> Seq(Set(316, 181), Set(316, 309, 305, 304)),
-    317  -> Seq(Set(317, 315, 313, 310)),
-    318  -> Seq(Set(318, 313, 312, 310)),
-    319  -> Seq(Set(319, 283), Set(319, 318, 317, 308)),
-    320  -> Seq(Set(320, 319, 317, 316)),
-    321  -> Seq(Set(321, 290), Set(321, 319, 316, 314)),
-    322  -> Seq(Set(322, 255), Set(322, 321, 320, 305)),
-    323  -> Seq(Set(323, 322, 320, 313)),
-    324  -> Seq(Set(324, 321, 320, 318)),
-    325  -> Seq(Set(325, 323, 320, 315)),
-    326  -> Seq(Set(326, 325, 323, 316)),
-    327  -> Seq(Set(327, 293), Set(327, 325, 322, 319)),
-    328  -> Seq(Set(328, 323, 321, 319)),
-    329  -> Seq(Set(329, 279), Set(329, 326, 323, 321)),
-    330  -> Seq(Set(330, 328, 323, 322)),
-    331  -> Seq(Set(331, 329, 325, 321)),
-    332  -> Seq(Set(332, 209), Set(332, 325, 321, 320)),
-    333  -> Seq(Set(333, 331), Set(333, 331, 329, 325)),
-    334  -> Seq(Set(334, 333, 330, 327)),
-    335  -> Seq(Set(335, 333, 328, 325)),
-    336  -> Seq(Set(336, 335, 332, 329)),
-    337  -> Seq(Set(337, 282), Set(337, 336, 331, 327)),
-    338  -> Seq(Set(338, 336, 335, 332)),
-    339  -> Seq(Set(339, 332, 329, 323)),
-    340  -> Seq(Set(340, 337, 336, 329)),
-    341  -> Seq(Set(341, 336, 330, 327)),
-    342  -> Seq(Set(342, 217), Set(342, 341, 340, 331)),
-    343  -> Seq(Set(343, 268), Set(343, 338, 335, 333)),
-    344  -> Seq(Set(344, 338, 334, 333)),
-    345  -> Seq(Set(345, 323), Set(345, 343, 341, 337)),
-    346  -> Seq(Set(346, 344, 339, 335)),
-    347  -> Seq(Set(347, 344, 337, 336)),
-    348  -> Seq(Set(348, 344, 341, 340)),
-    349  -> Seq(Set(349, 347, 344, 343)),
-    350  -> Seq(Set(350, 297), Set(350, 340, 337, 336)),
-    351  -> Seq(Set(351, 317), Set(351, 348, 345, 343)),
-    352  -> Seq(Set(352, 346, 341, 339)),
-    353  -> Seq(Set(353, 284), Set(353, 349, 346, 344)),
-    354  -> Seq(Set(354, 349, 341, 340)),
-    355  -> Seq(Set(355, 354, 350, 349)),
-    356  -> Seq(Set(356, 349, 347, 346)),
-    357  -> Seq(Set(357, 355, 347, 346)),
-    358  -> Seq(Set(358, 351, 350, 344)),
-    359  -> Seq(Set(359, 291), Set(359, 358, 352, 350)),
-    360  -> Seq(Set(360, 359, 335, 334)),
-    361  -> Seq(Set(361, 360, 357, 354)),
-    362  -> Seq(Set(362, 299), Set(362, 360, 351, 344)),
-    363  -> Seq(Set(363, 362, 356, 355)),
-    364  -> Seq(Set(364, 297), Set(364, 363, 359, 352)),
-    365  -> Seq(Set(365, 360, 359, 356)),
-    366  -> Seq(Set(366, 337), Set(366, 362, 359, 352)),
-    367  -> Seq(Set(367, 346), Set(367, 365, 363, 358)),
-    368  -> Seq(Set(368, 361, 359, 351)),
-    369  -> Seq(Set(369, 278), Set(369, 367, 359, 358)),
-    370  -> Seq(Set(370, 231), Set(370, 368, 367, 365)),
-    371  -> Seq(Set(371, 369, 368, 363)),
-    372  -> Seq(Set(372, 369, 365, 357)),
-    373  -> Seq(Set(373, 371, 366, 365)),
-    374  -> Seq(Set(374, 369, 368, 366)),
-    375  -> Seq(Set(375, 359), Set(375, 374, 368, 367)),
-    376  -> Seq(Set(376, 371, 369, 368)),
-    377  -> Seq(Set(377, 336), Set(377, 376, 374, 369)),
-    378  -> Seq(Set(378, 335), Set(378, 374, 365, 363)),
-    379  -> Seq(Set(379, 375, 370, 369)),
-    380  -> Seq(Set(380, 333), Set(380, 377, 374, 366)),
-    381  -> Seq(Set(381, 380, 379, 376)),
-    382  -> Seq(Set(382, 301), Set(382, 379, 375, 364)),
-    383  -> Seq(Set(383, 293), Set(383, 382, 378, 374)),
-    384  -> Seq(Set(384, 378, 369, 368)),
-    385  -> Seq(Set(385, 379), Set(385, 383, 381, 379)),
-    386  -> Seq(Set(386, 303), Set(386, 381, 380, 376)),
-    387  -> Seq(Set(387, 385, 379, 378)),
-    388  -> Seq(Set(388, 387, 385, 374)),
-    389  -> Seq(Set(389, 384, 380, 379)),
-    390  -> Seq(Set(390, 301), Set(390, 388, 380, 377)),
-    391  -> Seq(Set(391, 363), Set(391, 390, 389, 385)),
-    392  -> Seq(Set(392, 386, 382, 379)),
-    393  -> Seq(Set(393, 386), Set(393, 392, 391, 386)),
-    394  -> Seq(Set(394, 259), Set(394, 392, 387, 386)) )
+    2 -> Seq(Set(2, 1)),
+    3 -> Seq(Set(3, 2)),
+    4 -> Seq(Set(4, 3)),
+    5 -> Seq(Set(5, 3), Set(5, 4, 3, 2)),
+    6 -> Seq(Set(6, 5), Set(6, 5, 3, 2)),
+    7 -> Seq(Set(7, 6), Set(7, 6, 5, 4)),
+    8 -> Seq(Set(8, 6, 5, 4)),
+    9 -> Seq(Set(9, 5), Set(9, 8, 6, 5)),
+    10 -> Seq(Set(10, 7), Set(10, 9, 7, 6)),
+    11 -> Seq(Set(11, 9), Set(11, 10, 9, 7)),
+    12 -> Seq(Set(12, 11, 8, 6)),
+    13 -> Seq(Set(13, 12, 10, 9)),
+    14 -> Seq(Set(14, 13, 11, 9)),
+    15 -> Seq(Set(15, 14), Set(15, 14, 13, 11)),
+    16 -> Seq(Set(16, 14, 13, 11)),
+    17 -> Seq(Set(17, 14), Set(17, 16, 15, 14)),
+    18 -> Seq(Set(18, 11), Set(18, 17, 16, 13)),
+    19 -> Seq(Set(19, 18, 17, 14)),
+    20 -> Seq(Set(20, 17), Set(20, 19, 16, 14)),
+    21 -> Seq(Set(21, 19), Set(21, 20, 19, 16)),
+    22 -> Seq(Set(22, 21), Set(22, 19, 18, 17)),
+    23 -> Seq(Set(23, 18), Set(23, 22, 20, 18)),
+    24 -> Seq(Set(24, 23, 21, 20)),
+    25 -> Seq(Set(25, 22), Set(25, 24, 23, 22)),
+    26 -> Seq(Set(26, 25, 24, 20)),
+    27 -> Seq(Set(27, 26, 25, 22)),
+    28 -> Seq(Set(28, 25), Set(28, 27, 24, 22)),
+    29 -> Seq(Set(29, 27), Set(29, 28, 27, 25)),
+    30 -> Seq(Set(30, 29, 26, 24)),
+    31 -> Seq(Set(31, 28), Set(31, 30, 29, 28)),
+    32 -> Seq(Set(32, 30, 26, 25)),
+    33 -> Seq(Set(33, 20), Set(33, 32, 29, 27)),
+    34 -> Seq(Set(34, 31, 30, 26)),
+    35 -> Seq(Set(35, 33), Set(35, 34, 28, 27)),
+    36 -> Seq(Set(36, 25), Set(36, 35, 29, 28)),
+    37 -> Seq(Set(37, 36, 33, 31)),
+    38 -> Seq(Set(38, 37, 33, 32)),
+    39 -> Seq(Set(39, 35), Set(39, 38, 35, 32)),
+    40 -> Seq(Set(40, 37, 36, 35)),
+    41 -> Seq(Set(41, 38), Set(41, 40, 39, 38)),
+    42 -> Seq(Set(42, 40, 37, 35)),
+    43 -> Seq(Set(43, 42, 38, 37)),
+    44 -> Seq(Set(44, 42, 39, 38)),
+    45 -> Seq(Set(45, 44, 42, 41)),
+    46 -> Seq(Set(46, 40, 39, 38)),
+    47 -> Seq(Set(47, 42), Set(47, 46, 43, 42)),
+    48 -> Seq(Set(48, 44, 41, 39)),
+    49 -> Seq(Set(49, 40), Set(49, 45, 44, 43)),
+    50 -> Seq(Set(50, 48, 47, 46)),
+    51 -> Seq(Set(51, 50, 48, 45)),
+    52 -> Seq(Set(52, 49), Set(52, 51, 49, 46)),
+    53 -> Seq(Set(53, 52, 51, 47)),
+    54 -> Seq(Set(54, 51, 48, 46)),
+    55 -> Seq(Set(55, 31), Set(55, 54, 53, 49)),
+    56 -> Seq(Set(56, 54, 52, 49)),
+    57 -> Seq(Set(57, 50), Set(57, 55, 54, 52)),
+    58 -> Seq(Set(58, 39), Set(58, 57, 53, 52)),
+    59 -> Seq(Set(59, 57, 55, 52)),
+    60 -> Seq(Set(60, 59), Set(60, 58, 56, 55)),
+    61 -> Seq(Set(61, 60, 59, 56)),
+    62 -> Seq(Set(62, 59, 57, 56)),
+    63 -> Seq(Set(63, 62), Set(63, 62, 59, 58)),
+    64 -> Seq(Set(64, 63, 61, 60)),
+    65 -> Seq(Set(65, 47), Set(65, 64, 62, 61)),
+    66 -> Seq(Set(66, 60, 58, 57)),
+    67 -> Seq(Set(67, 66, 65, 62)),
+    68 -> Seq(Set(68, 59), Set(68, 67, 63, 61)),
+    69 -> Seq(Set(69, 67, 64, 63)),
+    70 -> Seq(Set(70, 69, 67, 65)),
+    71 -> Seq(Set(71, 65), Set(71, 70, 68, 66)),
+    72 -> Seq(Set(72, 69, 63, 62)),
+    73 -> Seq(Set(73, 48), Set(73, 71, 70, 69)),
+    74 -> Seq(Set(74, 71, 70, 67)),
+    75 -> Seq(Set(75, 74, 72, 69)),
+    76 -> Seq(Set(76, 74, 72, 71)),
+    77 -> Seq(Set(77, 75, 72, 71)),
+    78 -> Seq(Set(78, 77, 76, 71)),
+    79 -> Seq(Set(79, 70), Set(79, 77, 76, 75)),
+    80 -> Seq(Set(80, 78, 76, 71)),
+    81 -> Seq(Set(81, 77), Set(81, 79, 78, 75)),
+    82 -> Seq(Set(82, 78, 76, 73)),
+    83 -> Seq(Set(83, 81, 79, 76)),
+    84 -> Seq(Set(84, 71), Set(84, 83, 77, 75)),
+    85 -> Seq(Set(85, 84, 83, 77)),
+    86 -> Seq(Set(86, 84, 81, 80)),
+    87 -> Seq(Set(87, 74), Set(87, 86, 82, 80)),
+    88 -> Seq(Set(88, 80, 79, 77)),
+    89 -> Seq(Set(89, 51), Set(89, 86, 84, 83)),
+    90 -> Seq(Set(90, 88, 87, 85)),
+    91 -> Seq(Set(91, 90, 86, 83)),
+    92 -> Seq(Set(92, 90, 87, 86)),
+    93 -> Seq(Set(93, 91), Set(93, 91, 90, 87)),
+    94 -> Seq(Set(94, 73), Set(94, 93, 89, 88)),
+    95 -> Seq(Set(95, 84), Set(95, 94, 90, 88)),
+    96 -> Seq(Set(96, 90, 87, 86)),
+    97 -> Seq(Set(97, 91), Set(97, 95, 93, 91)),
+    98 -> Seq(Set(98, 87), Set(98, 97, 91, 90)),
+    99 -> Seq(Set(99, 95, 94, 92)),
+    100 -> Seq(Set(100, 63), Set(100, 98, 93, 92)),
+    101 -> Seq(Set(101, 100, 95, 94)),
+    102 -> Seq(Set(102, 99, 97, 96)),
+    103 -> Seq(Set(103, 94), Set(103, 102, 99, 94)),
+    104 -> Seq(Set(104, 103, 94, 93)),
+    105 -> Seq(Set(105, 89), Set(105, 104, 99, 98)),
+    106 -> Seq(Set(106, 91), Set(106, 105, 101, 100)),
+    107 -> Seq(Set(107, 105, 99, 98)),
+    108 -> Seq(Set(108, 77), Set(108, 103, 97, 96)),
+    109 -> Seq(Set(109, 107, 105, 104)),
+    110 -> Seq(Set(110, 109, 106, 104)),
+    111 -> Seq(Set(111, 101), Set(111, 109, 107, 104)),
+    112 -> Seq(Set(112, 108, 106, 101)),
+    113 -> Seq(Set(113, 104), Set(113, 111, 110, 108)),
+    114 -> Seq(Set(114, 113, 112, 103)),
+    115 -> Seq(Set(115, 110, 108, 107)),
+    116 -> Seq(Set(116, 114, 111, 110)),
+    117 -> Seq(Set(117, 116, 115, 112)),
+    118 -> Seq(Set(118, 85), Set(118, 116, 113, 112)),
+    119 -> Seq(Set(119, 111), Set(119, 116, 111, 110)),
+    120 -> Seq(Set(120, 118, 114, 111)),
+    121 -> Seq(Set(121, 103), Set(121, 120, 116, 113)),
+    122 -> Seq(Set(122, 121, 120, 116)),
+    123 -> Seq(Set(123, 121), Set(123, 122, 119, 115)),
+    124 -> Seq(Set(124, 87), Set(124, 119, 118, 117)),
+    125 -> Seq(Set(125, 120, 119, 118)),
+    126 -> Seq(Set(126, 124, 122, 119)),
+    127 -> Seq(Set(127, 126), Set(127, 126, 124, 120)),
+    128 -> Seq(Set(128, 127, 126, 121)),
+    129 -> Seq(Set(129, 124), Set(129, 128, 125, 124)),
+    130 -> Seq(Set(130, 127), Set(130, 129, 128, 125)),
+    131 -> Seq(Set(131, 129, 128, 123)),
+    132 -> Seq(Set(132, 103), Set(132, 130, 127, 123)),
+    133 -> Seq(Set(133, 131, 125, 124)),
+    134 -> Seq(Set(134, 77), Set(134, 133, 129, 127)),
+    135 -> Seq(Set(135, 124), Set(135, 132, 131, 129)),
+    136 -> Seq(Set(136, 134, 133, 128)),
+    137 -> Seq(Set(137, 116), Set(137, 136, 133, 126)),
+    138 -> Seq(Set(138, 137, 131, 130)),
+    139 -> Seq(Set(139, 136, 134, 131)),
+    140 -> Seq(Set(140, 111), Set(140, 139, 136, 132)),
+    141 -> Seq(Set(141, 140, 135, 128)),
+    142 -> Seq(Set(142, 121), Set(142, 141, 139, 132)),
+    143 -> Seq(Set(143, 141, 140, 138)),
+    144 -> Seq(Set(144, 142, 140, 137)),
+    145 -> Seq(Set(145, 93), Set(145, 144, 140, 139)),
+    146 -> Seq(Set(146, 144, 143, 141)),
+    147 -> Seq(Set(147, 145, 143, 136)),
+    148 -> Seq(Set(148, 121), Set(148, 145, 143, 141)),
+    149 -> Seq(Set(149, 142, 140, 139)),
+    150 -> Seq(Set(150, 97), Set(150, 148, 147, 142)),
+    151 -> Seq(Set(151, 148), Set(151, 150, 149, 148)),
+    152 -> Seq(Set(152, 150, 149, 146)),
+    153 -> Seq(Set(153, 152), Set(153, 149, 148, 145)),
+    154 -> Seq(Set(154, 153, 149, 145)),
+    155 -> Seq(Set(155, 151, 150, 148)),
+    156 -> Seq(Set(156, 153, 151, 147)),
+    157 -> Seq(Set(157, 155, 152, 151)),
+    158 -> Seq(Set(158, 153, 152, 150)),
+    159 -> Seq(Set(159, 128), Set(159, 156, 153, 148)),
+    160 -> Seq(Set(160, 158, 157, 155)),
+    161 -> Seq(Set(161, 143), Set(161, 159, 158, 155)),
+    162 -> Seq(Set(162, 158, 155, 154)),
+    163 -> Seq(Set(163, 160, 157, 156)),
+    164 -> Seq(Set(164, 159, 158, 152)),
+    165 -> Seq(Set(165, 162, 157, 156)),
+    166 -> Seq(Set(166, 164, 163, 156)),
+    167 -> Seq(Set(167, 161), Set(167, 165, 163, 161)),
+    168 -> Seq(Set(168, 162, 159, 152)),
+    169 -> Seq(Set(169, 135), Set(169, 164, 163, 161)),
+    170 -> Seq(Set(170, 147), Set(170, 169, 166, 161)),
+    171 -> Seq(Set(171, 169, 166, 165)),
+    172 -> Seq(Set(172, 165), Set(172, 169, 165, 161)),
+    173 -> Seq(Set(173, 171, 168, 165)),
+    174 -> Seq(Set(174, 161), Set(174, 169, 166, 165)),
+    175 -> Seq(Set(175, 169), Set(175, 173, 171, 169)),
+    176 -> Seq(Set(176, 167, 165, 164)),
+    177 -> Seq(Set(177, 169), Set(177, 175, 174, 172)),
+    178 -> Seq(Set(178, 91), Set(178, 176, 171, 170)),
+    179 -> Seq(Set(179, 178, 177, 175)),
+    180 -> Seq(Set(180, 173, 170, 168)),
+    181 -> Seq(Set(181, 180, 175, 174)),
+    182 -> Seq(Set(182, 181, 176, 174)),
+    183 -> Seq(Set(183, 127), Set(183, 179, 176, 175)),
+    184 -> Seq(Set(184, 177, 176, 175)),
+    185 -> Seq(Set(185, 161), Set(185, 184, 182, 177)),
+    186 -> Seq(Set(186, 180, 178, 177)),
+    187 -> Seq(Set(187, 182, 181, 180)),
+    188 -> Seq(Set(188, 186, 183, 182)),
+    189 -> Seq(Set(189, 187, 184, 183)),
+    190 -> Seq(Set(190, 188, 184, 177)),
+    191 -> Seq(Set(191, 182), Set(191, 187, 185, 184)),
+    192 -> Seq(Set(192, 190, 178, 177)),
+    193 -> Seq(Set(193, 178), Set(193, 189, 186, 184)),
+    194 -> Seq(Set(194, 107), Set(194, 192, 191, 190)),
+    195 -> Seq(Set(195, 193, 192, 187)),
+    196 -> Seq(Set(196, 194, 187, 185)),
+    197 -> Seq(Set(197, 195, 193, 188)),
+    198 -> Seq(Set(198, 133), Set(198, 193, 190, 183)),
+    199 -> Seq(Set(199, 165), Set(199, 198, 195, 190)),
+    200 -> Seq(Set(200, 198, 197, 195)),
+    201 -> Seq(Set(201, 187), Set(201, 199, 198, 195)),
+    202 -> Seq(Set(202, 147), Set(202, 198, 196, 195)),
+    203 -> Seq(Set(203, 202, 196, 195)),
+    204 -> Seq(Set(204, 201, 200, 194)),
+    205 -> Seq(Set(205, 203, 200, 196)),
+    206 -> Seq(Set(206, 201, 197, 196)),
+    207 -> Seq(Set(207, 164), Set(207, 206, 201, 198)),
+    208 -> Seq(Set(208, 207, 205, 199)),
+    209 -> Seq(Set(209, 203), Set(209, 207, 206, 204)),
+    210 -> Seq(Set(210, 207, 206, 198)),
+    211 -> Seq(Set(211, 203, 201, 200)),
+    212 -> Seq(Set(212, 107), Set(212, 209, 208, 205)),
+    213 -> Seq(Set(213, 211, 208, 207)),
+    214 -> Seq(Set(214, 213, 211, 209)),
+    215 -> Seq(Set(215, 192), Set(215, 212, 210, 209)),
+    216 -> Seq(Set(216, 215, 213, 209)),
+    217 -> Seq(Set(217, 172), Set(217, 213, 212, 211)),
+    218 -> Seq(Set(218, 207), Set(218, 217, 211, 210)),
+    219 -> Seq(Set(219, 218, 215, 211)),
+    220 -> Seq(Set(220, 211, 210, 208)),
+    221 -> Seq(Set(221, 219, 215, 213)),
+    222 -> Seq(Set(222, 220, 217, 214)),
+    223 -> Seq(Set(223, 190), Set(223, 221, 219, 218)),
+    224 -> Seq(Set(224, 222, 217, 212)),
+    225 -> Seq(Set(225, 193), Set(225, 224, 220, 215)),
+    226 -> Seq(Set(226, 223, 219, 216)),
+    227 -> Seq(Set(227, 223, 218, 217)),
+    228 -> Seq(Set(228, 226, 217, 216)),
+    229 -> Seq(Set(229, 228, 225, 219)),
+    230 -> Seq(Set(230, 224, 223, 222)),
+    231 -> Seq(Set(231, 205), Set(231, 229, 227, 224)),
+    232 -> Seq(Set(232, 228, 223, 221)),
+    233 -> Seq(Set(233, 159), Set(233, 232, 229, 224)),
+    234 -> Seq(Set(234, 203), Set(234, 232, 225, 223)),
+    235 -> Seq(Set(235, 234, 229, 226)),
+    236 -> Seq(Set(236, 231), Set(236, 229, 228, 226)),
+    237 -> Seq(Set(237, 236, 233, 230)),
+    238 -> Seq(Set(238, 237, 236, 233)),
+    239 -> Seq(Set(239, 203), Set(239, 238, 232, 227)),
+    240 -> Seq(Set(240, 237, 235, 232)),
+    241 -> Seq(Set(241, 171), Set(241, 237, 233, 232)),
+    242 -> Seq(Set(242, 241, 236, 231)),
+    243 -> Seq(Set(243, 242, 238, 235)),
+    244 -> Seq(Set(244, 243, 240, 235)),
+    245 -> Seq(Set(245, 244, 241, 239)),
+    246 -> Seq(Set(246, 245, 244, 235)),
+    247 -> Seq(Set(247, 165), Set(247, 245, 243, 238)),
+    248 -> Seq(Set(248, 238, 234, 233)),
+    249 -> Seq(Set(249, 163), Set(249, 248, 245, 242)),
+    250 -> Seq(Set(250, 147), Set(250, 247, 245, 240)),
+    251 -> Seq(Set(251, 249, 247, 244)),
+    252 -> Seq(Set(252, 185), Set(252, 251, 247, 241)),
+    253 -> Seq(Set(253, 252, 247, 246)),
+    254 -> Seq(Set(254, 253, 252, 247)),
+    255 -> Seq(Set(255, 203), Set(255, 253, 252, 250)),
+    256 -> Seq(Set(256, 254, 251, 246)),
+    257 -> Seq(Set(257, 245), Set(257, 255, 251, 250)),
+    258 -> Seq(Set(258, 175), Set(258, 254, 252, 249)),
+    259 -> Seq(Set(259, 257, 253, 249)),
+    260 -> Seq(Set(260, 253, 252, 250)),
+    261 -> Seq(Set(261, 257, 255, 254)),
+    262 -> Seq(Set(262, 258, 254, 253)),
+    263 -> Seq(Set(263, 170), Set(263, 261, 258, 252)),
+    264 -> Seq(Set(264, 263, 255, 254)),
+    265 -> Seq(Set(265, 223), Set(265, 263, 262, 260)),
+    266 -> Seq(Set(266, 219), Set(266, 265, 260, 259)),
+    267 -> Seq(Set(267, 264, 261, 259)),
+    268 -> Seq(Set(268, 243), Set(268, 267, 264, 258)),
+    269 -> Seq(Set(269, 268, 263, 262)),
+    270 -> Seq(Set(270, 217), Set(270, 267, 263, 260)),
+    271 -> Seq(Set(271, 213), Set(271, 265, 264, 260)),
+    272 -> Seq(Set(272, 270, 266, 263)),
+    273 -> Seq(Set(273, 250), Set(273, 272, 271, 266)),
+    274 -> Seq(Set(274, 207), Set(274, 272, 267, 265)),
+    275 -> Seq(Set(275, 266, 265, 264)),
+    276 -> Seq(Set(276, 275, 273, 270)),
+    277 -> Seq(Set(277, 274, 271, 265)),
+    278 -> Seq(Set(278, 273), Set(278, 277, 274, 273)),
+    279 -> Seq(Set(279, 274), Set(279, 278, 275, 274)),
+    280 -> Seq(Set(280, 278, 275, 271)),
+    281 -> Seq(Set(281, 188), Set(281, 280, 277, 272)),
+    282 -> Seq(Set(282, 247), Set(282, 278, 277, 272)),
+    283 -> Seq(Set(283, 278, 276, 271)),
+    284 -> Seq(Set(284, 165), Set(284, 279, 278, 276)),
+    285 -> Seq(Set(285, 280, 278, 275)),
+    286 -> Seq(Set(286, 217), Set(286, 285, 276, 271)),
+    287 -> Seq(Set(287, 216), Set(287, 285, 282, 281)),
+    288 -> Seq(Set(288, 287, 278, 277)),
+    289 -> Seq(Set(289, 268), Set(289, 286, 285, 277)),
+    290 -> Seq(Set(290, 288, 287, 285)),
+    291 -> Seq(Set(291, 286, 280, 279)),
+    292 -> Seq(Set(292, 195), Set(292, 291, 289, 285)),
+    293 -> Seq(Set(293, 292, 287, 282)),
+    294 -> Seq(Set(294, 233), Set(294, 292, 291, 285)),
+    295 -> Seq(Set(295, 247), Set(295, 293, 291, 290)),
+    296 -> Seq(Set(296, 292, 287, 285)),
+    297 -> Seq(Set(297, 292), Set(297, 296, 293, 292)),
+    298 -> Seq(Set(298, 294, 290, 287)),
+    299 -> Seq(Set(299, 295, 293, 288)),
+    300 -> Seq(Set(300, 293), Set(300, 290, 288, 287)),
+    301 -> Seq(Set(301, 299, 296, 292)),
+    302 -> Seq(Set(302, 261), Set(302, 297, 293, 290)),
+    303 -> Seq(Set(303, 297, 291, 290)),
+    304 -> Seq(Set(304, 303, 302, 293)),
+    305 -> Seq(Set(305, 203), Set(305, 303, 299, 298)),
+    306 -> Seq(Set(306, 305, 303, 299)),
+    307 -> Seq(Set(307, 305, 303, 299)),
+    308 -> Seq(Set(308, 306, 299, 293)),
+    309 -> Seq(Set(309, 307, 302, 299)),
+    310 -> Seq(Set(310, 309, 305, 302)),
+    311 -> Seq(Set(311, 308, 306, 304)),
+    312 -> Seq(Set(312, 307, 302, 301)),
+    313 -> Seq(Set(313, 234), Set(313, 312, 310, 306)),
+    314 -> Seq(Set(314, 299), Set(314, 311, 305, 300)),
+    315 -> Seq(Set(315, 314, 306, 305)),
+    316 -> Seq(Set(316, 181), Set(316, 309, 305, 304)),
+    317 -> Seq(Set(317, 315, 313, 310)),
+    318 -> Seq(Set(318, 313, 312, 310)),
+    319 -> Seq(Set(319, 283), Set(319, 318, 317, 308)),
+    320 -> Seq(Set(320, 319, 317, 316)),
+    321 -> Seq(Set(321, 290), Set(321, 319, 316, 314)),
+    322 -> Seq(Set(322, 255), Set(322, 321, 320, 305)),
+    323 -> Seq(Set(323, 322, 320, 313)),
+    324 -> Seq(Set(324, 321, 320, 318)),
+    325 -> Seq(Set(325, 323, 320, 315)),
+    326 -> Seq(Set(326, 325, 323, 316)),
+    327 -> Seq(Set(327, 293), Set(327, 325, 322, 319)),
+    328 -> Seq(Set(328, 323, 321, 319)),
+    329 -> Seq(Set(329, 279), Set(329, 326, 323, 321)),
+    330 -> Seq(Set(330, 328, 323, 322)),
+    331 -> Seq(Set(331, 329, 325, 321)),
+    332 -> Seq(Set(332, 209), Set(332, 325, 321, 320)),
+    333 -> Seq(Set(333, 331), Set(333, 331, 329, 325)),
+    334 -> Seq(Set(334, 333, 330, 327)),
+    335 -> Seq(Set(335, 333, 328, 325)),
+    336 -> Seq(Set(336, 335, 332, 329)),
+    337 -> Seq(Set(337, 282), Set(337, 336, 331, 327)),
+    338 -> Seq(Set(338, 336, 335, 332)),
+    339 -> Seq(Set(339, 332, 329, 323)),
+    340 -> Seq(Set(340, 337, 336, 329)),
+    341 -> Seq(Set(341, 336, 330, 327)),
+    342 -> Seq(Set(342, 217), Set(342, 341, 340, 331)),
+    343 -> Seq(Set(343, 268), Set(343, 338, 335, 333)),
+    344 -> Seq(Set(344, 338, 334, 333)),
+    345 -> Seq(Set(345, 323), Set(345, 343, 341, 337)),
+    346 -> Seq(Set(346, 344, 339, 335)),
+    347 -> Seq(Set(347, 344, 337, 336)),
+    348 -> Seq(Set(348, 344, 341, 340)),
+    349 -> Seq(Set(349, 347, 344, 343)),
+    350 -> Seq(Set(350, 297), Set(350, 340, 337, 336)),
+    351 -> Seq(Set(351, 317), Set(351, 348, 345, 343)),
+    352 -> Seq(Set(352, 346, 341, 339)),
+    353 -> Seq(Set(353, 284), Set(353, 349, 346, 344)),
+    354 -> Seq(Set(354, 349, 341, 340)),
+    355 -> Seq(Set(355, 354, 350, 349)),
+    356 -> Seq(Set(356, 349, 347, 346)),
+    357 -> Seq(Set(357, 355, 347, 346)),
+    358 -> Seq(Set(358, 351, 350, 344)),
+    359 -> Seq(Set(359, 291), Set(359, 358, 352, 350)),
+    360 -> Seq(Set(360, 359, 335, 334)),
+    361 -> Seq(Set(361, 360, 357, 354)),
+    362 -> Seq(Set(362, 299), Set(362, 360, 351, 344)),
+    363 -> Seq(Set(363, 362, 356, 355)),
+    364 -> Seq(Set(364, 297), Set(364, 363, 359, 352)),
+    365 -> Seq(Set(365, 360, 359, 356)),
+    366 -> Seq(Set(366, 337), Set(366, 362, 359, 352)),
+    367 -> Seq(Set(367, 346), Set(367, 365, 363, 358)),
+    368 -> Seq(Set(368, 361, 359, 351)),
+    369 -> Seq(Set(369, 278), Set(369, 367, 359, 358)),
+    370 -> Seq(Set(370, 231), Set(370, 368, 367, 365)),
+    371 -> Seq(Set(371, 369, 368, 363)),
+    372 -> Seq(Set(372, 369, 365, 357)),
+    373 -> Seq(Set(373, 371, 366, 365)),
+    374 -> Seq(Set(374, 369, 368, 366)),
+    375 -> Seq(Set(375, 359), Set(375, 374, 368, 367)),
+    376 -> Seq(Set(376, 371, 369, 368)),
+    377 -> Seq(Set(377, 336), Set(377, 376, 374, 369)),
+    378 -> Seq(Set(378, 335), Set(378, 374, 365, 363)),
+    379 -> Seq(Set(379, 375, 370, 369)),
+    380 -> Seq(Set(380, 333), Set(380, 377, 374, 366)),
+    381 -> Seq(Set(381, 380, 379, 376)),
+    382 -> Seq(Set(382, 301), Set(382, 379, 375, 364)),
+    383 -> Seq(Set(383, 293), Set(383, 382, 378, 374)),
+    384 -> Seq(Set(384, 378, 369, 368)),
+    385 -> Seq(Set(385, 379), Set(385, 383, 381, 379)),
+    386 -> Seq(Set(386, 303), Set(386, 381, 380, 376)),
+    387 -> Seq(Set(387, 385, 379, 378)),
+    388 -> Seq(Set(388, 387, 385, 374)),
+    389 -> Seq(Set(389, 384, 380, 379)),
+    390 -> Seq(Set(390, 301), Set(390, 388, 380, 377)),
+    391 -> Seq(Set(391, 363), Set(391, 390, 389, 385)),
+    392 -> Seq(Set(392, 386, 382, 379)),
+    393 -> Seq(Set(393, 386), Set(393, 392, 391, 386)),
+    394 -> Seq(Set(394, 259), Set(394, 392, 387, 386))
+  )
 
   /** Second portion of known taps (a combined map hits the 64KB JVM method limit) */
   private def tapsSecond = Map(
-    395  -> Seq(Set(395, 390, 389, 384)),
-    396  -> Seq(Set(396, 371), Set(396, 392, 390, 389)),
-    397  -> Seq(Set(397, 392, 387, 385)),
-    398  -> Seq(Set(398, 393, 392, 384)),
-    399  -> Seq(Set(399, 313), Set(399, 397, 390, 388)),
-    400  -> Seq(Set(400, 398, 397, 395)),
-    401  -> Seq(Set(401, 249), Set(401, 399, 392, 389)),
-    402  -> Seq(Set(402, 399, 398, 393)),
-    403  -> Seq(Set(403, 398, 395, 394)),
-    404  -> Seq(Set(404, 215), Set(404, 400, 398, 397)),
-    405  -> Seq(Set(405, 398, 397, 388)),
-    406  -> Seq(Set(406, 249), Set(406, 402, 397, 393)),
-    407  -> Seq(Set(407, 336), Set(407, 402, 400, 398)),
-    408  -> Seq(Set(408, 407, 403, 401)),
-    409  -> Seq(Set(409, 322), Set(409, 406, 404, 402)),
-    410  -> Seq(Set(410, 407, 406, 400)),
-    411  -> Seq(Set(411, 408, 401, 399)),
-    412  -> Seq(Set(412, 265), Set(412, 409, 404, 401)),
-    413  -> Seq(Set(413, 407, 406, 403)),
-    414  -> Seq(Set(414, 405, 401, 398)),
-    415  -> Seq(Set(415, 313), Set(415, 413, 411, 406)),
-    416  -> Seq(Set(416, 414, 411, 407)),
-    417  -> Seq(Set(417, 310), Set(417, 416, 414, 407)),
-    418  -> Seq(Set(418, 417, 415, 403)),
-    419  -> Seq(Set(419, 415, 414, 404)),
-    420  -> Seq(Set(420, 412, 410, 407)),
-    421  -> Seq(Set(421, 419, 417, 416)),
-    422  -> Seq(Set(422, 273), Set(422, 421, 416, 412)),
-    423  -> Seq(Set(423, 398), Set(423, 420, 418, 414)),
-    424  -> Seq(Set(424, 422, 417, 415)),
-    425  -> Seq(Set(425, 413), Set(425, 422, 421, 418)),
-    426  -> Seq(Set(426, 415, 414, 412)),
-    427  -> Seq(Set(427, 422, 421, 416)),
-    428  -> Seq(Set(428, 323), Set(428, 426, 425, 417)),
-    429  -> Seq(Set(429, 422, 421, 419)),
-    430  -> Seq(Set(430, 419, 417, 415)),
-    431  -> Seq(Set(431, 311), Set(431, 430, 428, 426)),
-    432  -> Seq(Set(432, 429, 428, 419)),
-    433  -> Seq(Set(433, 400), Set(433, 430, 428, 422)),
-    434  -> Seq(Set(434, 429, 423, 422)),
-    435  -> Seq(Set(435, 430, 426, 423)),
-    436  -> Seq(Set(436, 271), Set(436, 432, 431, 430)),
-    437  -> Seq(Set(437, 436, 435, 431)),
-    438  -> Seq(Set(438, 373), Set(438, 436, 432, 421)),
-    439  -> Seq(Set(439, 390), Set(439, 437, 436, 431)),
-    440  -> Seq(Set(440, 439, 437, 436)),
-    441  -> Seq(Set(441, 410), Set(441, 440, 433, 430)),
-    442  -> Seq(Set(442, 440, 437, 435)),
-    443  -> Seq(Set(443, 442, 437, 433)),
-    444  -> Seq(Set(444, 435, 432, 431)),
-    445  -> Seq(Set(445, 441, 439, 438)),
-    446  -> Seq(Set(446, 341), Set(446, 442, 439, 431)),
-    447  -> Seq(Set(447, 374), Set(447, 446, 441, 438)),
-    448  -> Seq(Set(448, 444, 442, 437)),
-    449  -> Seq(Set(449, 315), Set(449, 446, 440, 438)),
-    450  -> Seq(Set(450, 371), Set(450, 443, 438, 434)),
-    451  -> Seq(Set(451, 450, 441, 435)),
-    452  -> Seq(Set(452, 448, 447, 446)),
-    453  -> Seq(Set(453, 449, 447, 438)),
-    454  -> Seq(Set(454, 449, 445, 444)),
-    455  -> Seq(Set(455, 417), Set(455, 453, 449, 444)),
-    456  -> Seq(Set(456, 454, 445, 433)),
-    457  -> Seq(Set(457, 441), Set(457, 454, 449, 446)),
-    458  -> Seq(Set(458, 255), Set(458, 453, 448, 445)),
-    459  -> Seq(Set(459, 457, 454, 447)),
-    460  -> Seq(Set(460, 399), Set(460, 459, 455, 451)),
-    461  -> Seq(Set(461, 460, 455, 454)),
-    462  -> Seq(Set(462, 389), Set(462, 457, 451, 450)),
-    463  -> Seq(Set(463, 370), Set(463, 456, 455, 452)),
-    464  -> Seq(Set(464, 460, 455, 441)),
-    465  -> Seq(Set(465, 406), Set(465, 463, 462, 457)),
-    466  -> Seq(Set(466, 460, 455, 452)),
-    467  -> Seq(Set(467, 466, 461, 456)),
-    468  -> Seq(Set(468, 464, 459, 453)),
-    469  -> Seq(Set(469, 467, 464, 460)),
-    470  -> Seq(Set(470, 321), Set(470, 468, 462, 461)),
-    471  -> Seq(Set(471, 470), Set(471, 469, 468, 465)),
-    472  -> Seq(Set(472, 470, 469, 461)),
-    473  -> Seq(Set(473, 470, 467, 465)),
-    474  -> Seq(Set(474, 283), Set(474, 465, 463, 456)),
-    475  -> Seq(Set(475, 471, 467, 466)),
-    476  -> Seq(Set(476, 461), Set(476, 475, 468, 466)),
-    477  -> Seq(Set(477, 470, 462, 461)),
-    478  -> Seq(Set(478, 357), Set(478, 477, 474, 472)),
-    479  -> Seq(Set(479, 375), Set(479, 475, 472, 470)),
-    480  -> Seq(Set(480, 473, 467, 464)),
-    481  -> Seq(Set(481, 343), Set(481, 480, 472, 471)),
-    482  -> Seq(Set(482, 477, 476, 473)),
-    483  -> Seq(Set(483, 479, 477, 474)),
-    484  -> Seq(Set(484, 379), Set(484, 483, 482, 470)),
-    485  -> Seq(Set(485, 479, 469, 468)),
-    486  -> Seq(Set(486, 481, 478, 472)),
-    487  -> Seq(Set(487, 393), Set(487, 485, 483, 478)),
-    488  -> Seq(Set(488, 487, 485, 484)),
-    489  -> Seq(Set(489, 406), Set(489, 484, 483, 480)),
-    490  -> Seq(Set(490, 271), Set(490, 485, 483, 481)),
-    491  -> Seq(Set(491, 488, 485, 480)),
-    492  -> Seq(Set(492, 491, 485, 484)),
-    493  -> Seq(Set(493, 490, 488, 483)),
-    494  -> Seq(Set(494, 357), Set(494, 493, 489, 481)),
-    495  -> Seq(Set(495, 419), Set(495, 494, 486, 480)),
-    496  -> Seq(Set(496, 494, 491, 480)),
-    497  -> Seq(Set(497, 419), Set(497, 493, 488, 486)),
-    498  -> Seq(Set(498, 495, 489, 487)),
-    499  -> Seq(Set(499, 494, 493, 488)),
-    500  -> Seq(Set(500, 499, 494, 490)),
-    501  -> Seq(Set(501, 499, 497, 496)),
-    502  -> Seq(Set(502, 498, 497, 494)),
-    503  -> Seq(Set(503, 500), Set(503, 502, 501, 500)),
-    504  -> Seq(Set(504, 502, 490, 483)),
-    505  -> Seq(Set(505, 349), Set(505, 500, 497, 493)),
-    506  -> Seq(Set(506, 411), Set(506, 501, 494, 491)),
-    507  -> Seq(Set(507, 504, 501, 494)),
-    508  -> Seq(Set(508, 399), Set(508, 505, 500, 495)),
-    509  -> Seq(Set(509, 506, 502, 501)),
-    510  -> Seq(Set(510, 501, 500, 498)),
-    511  -> Seq(Set(511, 501), Set(511, 509, 503, 501)),
-    512  -> Seq(Set(512, 510, 507, 504)),
-    513  -> Seq(Set(513, 428), Set(513, 505, 503, 500)),
-    514  -> Seq(Set(514, 511, 509, 507)),
-    515  -> Seq(Set(515, 511, 508, 501)),
-    516  -> Seq(Set(516, 514, 511, 509)),
-    517  -> Seq(Set(517, 515, 507, 505)),
-    518  -> Seq(Set(518, 485), Set(518, 516, 515, 507)),
-    519  -> Seq(Set(519, 440), Set(519, 517, 511, 507)),
-    520  -> Seq(Set(520, 509, 507, 503)),
-    521  -> Seq(Set(521, 489), Set(521, 519, 514, 512)),
-    522  -> Seq(Set(522, 518, 509, 507)),
-    523  -> Seq(Set(523, 521, 517, 510)),
-    524  -> Seq(Set(524, 357), Set(524, 523, 519, 515)),
-    525  -> Seq(Set(525, 524, 521, 519)),
-    526  -> Seq(Set(526, 525, 521, 517)),
-    527  -> Seq(Set(527, 480), Set(527, 526, 520, 518)),
-    528  -> Seq(Set(528, 526, 522, 517)),
-    529  -> Seq(Set(529, 487), Set(529, 528, 525, 522)),
-    530  -> Seq(Set(530, 527, 523, 520)),
-    531  -> Seq(Set(531, 529, 525, 519)),
-    532  -> Seq(Set(532, 531), Set(532, 529, 528, 522)),
-    533  -> Seq(Set(533, 531, 530, 529)),
-    534  -> Seq(Set(534, 533, 529, 527)),
-    535  -> Seq(Set(535, 533, 529, 527)),
-    536  -> Seq(Set(536, 533, 531, 529)),
-    537  -> Seq(Set(537, 443), Set(537, 536, 535, 527)),
-    538  -> Seq(Set(538, 537, 536, 533)),
-    539  -> Seq(Set(539, 535, 534, 529)),
-    540  -> Seq(Set(540, 361), Set(540, 537, 534, 529)),
-    541  -> Seq(Set(541, 537, 531, 528)),
-    542  -> Seq(Set(542, 540, 539, 533)),
-    543  -> Seq(Set(543, 527), Set(543, 538, 536, 532)),
-    544  -> Seq(Set(544, 538, 535, 531)),
-    545  -> Seq(Set(545, 423), Set(545, 539, 537, 532)),
-    546  -> Seq(Set(546, 545, 544, 538)),
-    547  -> Seq(Set(547, 543, 540, 534)),
-    548  -> Seq(Set(548, 545, 543, 538)),
-    549  -> Seq(Set(549, 546, 545, 533)),
-    550  -> Seq(Set(550, 357), Set(550, 546, 533, 529)),
-    551  -> Seq(Set(551, 416), Set(551, 550, 547, 542)),
-    552  -> Seq(Set(552, 550, 547, 532)),
-    553  -> Seq(Set(553, 514), Set(553, 550, 549, 542)),
-    554  -> Seq(Set(554, 551, 546, 543)),
-    555  -> Seq(Set(555, 551, 546, 545)),
-    556  -> Seq(Set(556, 403), Set(556, 549, 546, 540)),
-    557  -> Seq(Set(557, 552, 551, 550)),
-    558  -> Seq(Set(558, 553, 549, 544)),
-    559  -> Seq(Set(559, 525), Set(559, 557, 552, 550)),
-    560  -> Seq(Set(560, 554, 551, 549)),
-    561  -> Seq(Set(561, 490), Set(561, 558, 552, 550)),
-    562  -> Seq(Set(562, 560, 558, 551)),
-    563  -> Seq(Set(563, 561, 554, 549)),
-    564  -> Seq(Set(564, 401), Set(564, 563, 561, 558)),
-    565  -> Seq(Set(565, 564, 559, 554)),
-    566  -> Seq(Set(566, 413), Set(566, 564, 561, 560)),
-    567  -> Seq(Set(567, 424), Set(567, 563, 557, 556)),
-    568  -> Seq(Set(568, 558, 557, 551)),
-    569  -> Seq(Set(569, 492), Set(569, 568, 559, 557)),
-    570  -> Seq(Set(570, 503), Set(570, 563, 558, 552)),
-    571  -> Seq(Set(571, 569, 566, 561)),
-    572  -> Seq(Set(572, 571, 564, 560)),
-    573  -> Seq(Set(573, 569, 567, 563)),
-    574  -> Seq(Set(574, 561), Set(574, 569, 565, 560)),
-    575  -> Seq(Set(575, 429), Set(575, 572, 570, 569)),
-    576  -> Seq(Set(576, 573, 572, 563)),
-    577  -> Seq(Set(577, 552), Set(577, 575, 574, 569)),
-    578  -> Seq(Set(578, 562, 556, 555)),
-    579  -> Seq(Set(579, 572, 570, 567)),
-    580  -> Seq(Set(580, 579, 576, 574)),
-    581  -> Seq(Set(581, 575, 574, 568)),
-    582  -> Seq(Set(582, 497), Set(582, 579, 576, 571)),
-    583  -> Seq(Set(583, 453), Set(583, 581, 577, 575)),
-    584  -> Seq(Set(584, 581, 571, 570)),
-    585  -> Seq(Set(585, 464), Set(585, 583, 582, 577)),
-    586  -> Seq(Set(586, 584, 581, 579)),
-    587  -> Seq(Set(587, 586, 581, 576)),
-    588  -> Seq(Set(588, 437), Set(588, 577, 572, 571)),
-    589  -> Seq(Set(589, 586, 585, 579)),
-    590  -> Seq(Set(590, 497), Set(590, 588, 587, 578)),
-    591  -> Seq(Set(591, 587, 585, 582)),
-    592  -> Seq(Set(592, 591, 573, 568)),
-    593  -> Seq(Set(593, 507), Set(593, 588, 585, 584)),
-    594  -> Seq(Set(594, 575), Set(594, 586, 584, 583)),
-    595  -> Seq(Set(595, 594, 593, 586)),
-    596  -> Seq(Set(596, 592, 591, 590)),
-    597  -> Seq(Set(597, 588, 585, 583)),
-    598  -> Seq(Set(598, 597, 592, 591)),
-    599  -> Seq(Set(599, 569), Set(599, 593, 591, 590)),
-    600  -> Seq(Set(600, 599, 590, 589)),
-    601  -> Seq(Set(601, 400), Set(601, 600, 597, 589)),
-    602  -> Seq(Set(602, 596, 594, 591)),
-    603  -> Seq(Set(603, 600, 599, 597)),
-    604  -> Seq(Set(604, 600, 598, 589)),
-    605  -> Seq(Set(605, 600, 598, 595)),
-    606  -> Seq(Set(606, 602, 599, 591)),
-    607  -> Seq(Set(607, 502), Set(607, 600, 598, 595)),
-    608  -> Seq(Set(608, 606, 602, 585)),
-    609  -> Seq(Set(609, 578), Set(609, 601, 600, 597)),
-    610  -> Seq(Set(610, 483), Set(610, 602, 600, 599)),
-    611  -> Seq(Set(611, 609, 607, 601)),
-    612  -> Seq(Set(612, 607, 602, 598)),
-    613  -> Seq(Set(613, 609, 603, 594)),
-    614  -> Seq(Set(614, 613, 612, 607)),
-    615  -> Seq(Set(615, 404), Set(615, 614, 609, 608)),
-    616  -> Seq(Set(616, 614, 602, 597)),
-    617  -> Seq(Set(617, 417), Set(617, 612, 608, 607)),
-    618  -> Seq(Set(618, 615, 604, 598)),
-    619  -> Seq(Set(619, 614, 611, 610)),
-    620  -> Seq(Set(620, 619, 618, 611)),
-    621  -> Seq(Set(621, 616, 615, 609)),
-    622  -> Seq(Set(622, 325), Set(622, 612, 610, 605)),
-    623  -> Seq(Set(623, 555), Set(623, 614, 613, 612)),
-    624  -> Seq(Set(624, 617, 615, 612)),
-    625  -> Seq(Set(625, 492), Set(625, 620, 617, 613)),
-    626  -> Seq(Set(626, 623, 621, 613)),
-    627  -> Seq(Set(627, 622, 617, 613)),
-    628  -> Seq(Set(628, 405), Set(628, 626, 617, 616)),
-    629  -> Seq(Set(629, 627, 624, 623)),
-    630  -> Seq(Set(630, 628, 626, 623)),
-    631  -> Seq(Set(631, 324), Set(631, 625, 623, 617)),
-    632  -> Seq(Set(632, 629, 619, 613)),
-    633  -> Seq(Set(633, 532), Set(633, 632, 631, 626)),
-    634  -> Seq(Set(634, 319), Set(634, 631, 629, 627)),
-    635  -> Seq(Set(635, 631, 625, 621)),
-    636  -> Seq(Set(636, 632, 628, 623)),
-    637  -> Seq(Set(637, 636, 628, 623)),
-    638  -> Seq(Set(638, 637, 633, 632)),
-    639  -> Seq(Set(639, 623), Set(639, 636, 635, 629)),
-    640  -> Seq(Set(640, 638, 637, 626)),
-    641  -> Seq(Set(641, 630), Set(641, 640, 636, 622)),
-    642  -> Seq(Set(642, 523), Set(642, 636, 633, 632)),
-    643  -> Seq(Set(643, 641, 640, 632)),
-    644  -> Seq(Set(644, 634, 633, 632)),
-    645  -> Seq(Set(645, 641, 637, 634)),
-    646  -> Seq(Set(646, 397), Set(646, 635, 634, 633)),
-    647  -> Seq(Set(647, 642), Set(647, 646, 643, 642)),
-    648  -> Seq(Set(648, 647, 626, 625)),
-    649  -> Seq(Set(649, 612), Set(649, 648, 644, 638)),
-    650  -> Seq(Set(650, 647), Set(650, 644, 635, 632)),
-    651  -> Seq(Set(651, 646, 638, 637)),
-    652  -> Seq(Set(652, 559), Set(652, 647, 643, 641)),
-    653  -> Seq(Set(653, 646, 645, 643)),
-    654  -> Seq(Set(654, 649, 643, 640)),
-    655  -> Seq(Set(655, 567), Set(655, 653, 639, 638)),
-    656  -> Seq(Set(656, 646, 638, 637)),
-    657  -> Seq(Set(657, 619), Set(657, 656, 650, 649)),
-    658  -> Seq(Set(658, 603), Set(658, 651, 648, 646)),
-    659  -> Seq(Set(659, 657, 655, 644)),
-    660  -> Seq(Set(660, 657, 656, 648)),
-    661  -> Seq(Set(661, 657, 650, 649)),
-    662  -> Seq(Set(662, 365), Set(662, 659, 656, 650)),
-    663  -> Seq(Set(663, 406), Set(663, 655, 652, 649)),
-    664  -> Seq(Set(664, 662, 660, 649)),
-    665  -> Seq(Set(665, 632), Set(665, 661, 659, 654)),
-    666  -> Seq(Set(666, 664, 659, 656)),
-    667  -> Seq(Set(667, 664, 660, 649)),
-    668  -> Seq(Set(668, 658, 656, 651)),
-    669  -> Seq(Set(669, 667, 665, 664)),
-    670  -> Seq(Set(670, 517), Set(670, 669, 665, 664)),
-    671  -> Seq(Set(671, 656), Set(671, 669, 665, 662)),
-    672  -> Seq(Set(672, 667, 666, 661)),
-    673  -> Seq(Set(673, 645), Set(673, 666, 664, 663)),
-    674  -> Seq(Set(674, 671, 665, 660)),
-    675  -> Seq(Set(675, 674, 672, 669)),
-    676  -> Seq(Set(676, 435), Set(676, 675, 671, 664)),
-    677  -> Seq(Set(677, 674, 673, 669)),
-    678  -> Seq(Set(678, 675, 673, 663)),
-    679  -> Seq(Set(679, 613), Set(679, 676, 667, 661)),
-    680  -> Seq(Set(680, 679, 650, 645)),
-    681  -> Seq(Set(681, 678, 672, 670)),
-    682  -> Seq(Set(682, 681, 679, 675)),
-    683  -> Seq(Set(683, 682, 677, 672)),
-    684  -> Seq(Set(684, 681, 671, 666)),
-    685  -> Seq(Set(685, 684, 682, 681)),
-    686  -> Seq(Set(686, 489), Set(686, 684, 674, 673)),
-    687  -> Seq(Set(687, 674), Set(687, 682, 675, 673)),
-    688  -> Seq(Set(688, 682, 674, 669)),
-    689  -> Seq(Set(689, 675), Set(689, 686, 683, 681)),
-    690  -> Seq(Set(690, 687, 683, 680)),
-    691  -> Seq(Set(691, 689, 685, 678)),
-    692  -> Seq(Set(692, 393), Set(692, 687, 686, 678)),
-    693  -> Seq(Set(693, 691, 685, 678)),
-    694  -> Seq(Set(694, 691, 681, 677)),
-    695  -> Seq(Set(695, 483), Set(695, 694, 691, 686)),
-    696  -> Seq(Set(696, 694, 686, 673)),
-    697  -> Seq(Set(697, 430), Set(697, 689, 685, 681)),
-    698  -> Seq(Set(698, 483), Set(698, 690, 689, 688)),
-    699  -> Seq(Set(699, 698, 689, 684)),
-    700  -> Seq(Set(700, 698, 695, 694)),
-    701  -> Seq(Set(701, 699, 697, 685)),
-    702  -> Seq(Set(702, 665), Set(702, 701, 699, 695)),
-    703  -> Seq(Set(703, 702, 696, 691)),
-    704  -> Seq(Set(704, 701, 699, 692)),
-    705  -> Seq(Set(705, 686), Set(705, 704, 698, 697)),
-    706  -> Seq(Set(706, 697, 695, 692)),
-    707  -> Seq(Set(707, 702, 699, 692)),
-    708  -> Seq(Set(708, 421), Set(708, 706, 704, 703)),
-    709  -> Seq(Set(709, 708, 706, 705)),
-    710  -> Seq(Set(710, 709, 696, 695)),
-    711  -> Seq(Set(711, 619), Set(711, 704, 703, 700)),
-    712  -> Seq(Set(712, 709, 708, 707)),
-    713  -> Seq(Set(713, 672), Set(713, 706, 703, 696)),
-    714  -> Seq(Set(714, 691), Set(714, 709, 707, 701)),
-    715  -> Seq(Set(715, 714, 711, 708)),
-    716  -> Seq(Set(716, 533), Set(716, 706, 705, 704)),
-    717  -> Seq(Set(717, 716, 710, 701)),
-    718  -> Seq(Set(718, 717, 716, 713)),
-    719  -> Seq(Set(719, 569), Set(719, 711, 710, 707)),
-    720  -> Seq(Set(720, 718, 712, 709)),
-    721  -> Seq(Set(721, 712), Set(721, 720, 713, 712)),
-    722  -> Seq(Set(722, 491), Set(722, 721, 718, 707)),
-    723  -> Seq(Set(723, 717, 710, 707)),
-    724  -> Seq(Set(724, 719, 716, 711)),
-    725  -> Seq(Set(725, 720, 719, 716), Set(758)),
-    726  -> Seq(Set(726, 721), Set(726, 725, 722, 721)),
-    727  -> Seq(Set(727, 547), Set(727, 721, 719, 716)),
-    728  -> Seq(Set(728, 726, 725, 724), Set(761)),
-    729  -> Seq(Set(729, 671), Set(729, 726, 724, 718)),
-    730  -> Seq(Set(730, 583), Set(730, 726, 715, 711)),
-    731  -> Seq(Set(731, 729, 725, 723), Set(764)),
-    732  -> Seq(Set(732, 729, 728, 725), Set(765)),
-    733  -> Seq(Set(733, 731, 726, 725), Set(766)),
-    734  -> Seq(Set(734, 724, 721, 720), Set(767)),
-    735  -> Seq(Set(735, 691), Set(735, 733, 728, 727)),
-    736  -> Seq(Set(736, 730, 728, 723), Set(769)),
-    737  -> Seq(Set(737, 732), Set(737, 736, 733, 732)),
-    738  -> Seq(Set(738, 391), Set(738, 730, 729, 727)),
-    739  -> Seq(Set(739, 731, 723, 721), Set(772)),
-    740  -> Seq(Set(740, 587), Set(740, 737, 728, 716)),
-    741  -> Seq(Set(741, 738, 733, 732), Set(774)),
-    742  -> Seq(Set(742, 741, 738, 730), Set(775)),
-    743  -> Seq(Set(743, 653), Set(743, 742, 731, 730)),
-    744  -> Seq(Set(744, 743, 733, 731), Set(777)),
-    745  -> Seq(Set(745, 487), Set(745, 740, 738, 737)),
-    746  -> Seq(Set(746, 395), Set(746, 738, 733, 728)),
-    747  -> Seq(Set(747, 743, 741, 737), Set(780)),
-    748  -> Seq(Set(748, 744, 743, 733), Set(781)),
-    749  -> Seq(Set(749, 748, 743, 742), Set(782)),
-    750  -> Seq(Set(750, 746, 741, 734), Set(783)),
-    751  -> Seq(Set(751, 733), Set(751, 750, 748, 740)),
-    752  -> Seq(Set(752, 749, 732, 731), Set(785)),
-    753  -> Seq(Set(753, 595), Set(753, 748, 745, 740)),
-    754  -> Seq(Set(754, 735), Set(754, 742, 740, 735)),
-    755  -> Seq(Set(755, 754, 745, 743), Set(2048)),
-    756  -> Seq(Set(756, 407), Set(756, 755, 747, 740)),
-    757  -> Seq(Set(757, 756, 751, 750)),
-    758  -> Seq(Set(758, 757, 746, 741)),
-    759  -> Seq(Set(759, 661), Set(759, 757, 756, 750)),
-    760  -> Seq(Set(760, 757, 747, 734)),
-    761  -> Seq(Set(761, 758), Set(761, 760, 759, 758)),
-    762  -> Seq(Set(762, 679), Set(762, 761, 755, 745)),
-    763  -> Seq(Set(763, 754, 749, 747)),
-    764  -> Seq(Set(764, 761, 759, 758)),
-    765  -> Seq(Set(765, 760, 755, 754)),
-    766  -> Seq(Set(766, 757, 747, 744)),
-    767  -> Seq(Set(767, 599), Set(767, 763, 760, 759)),
-    768  -> Seq(Set(768, 764, 751, 749)),
-    769  -> Seq(Set(769, 649), Set(769, 763, 762, 760)),
-    770  -> Seq(Set(770, 768, 765, 756)),
-    771  -> Seq(Set(771, 765, 756, 754)),
-    772  -> Seq(Set(772, 765), Set(772, 767, 766, 764)),
-    773  -> Seq(Set(773, 767, 765, 763)),
-    774  -> Seq(Set(774, 589), Set(774, 767, 760, 758)),
-    775  -> Seq(Set(775, 408), Set(775, 771, 769, 768)),
-    776  -> Seq(Set(776, 773, 764, 759)),
-    777  -> Seq(Set(777, 748), Set(777, 776, 767, 761)),
-    778  -> Seq(Set(778, 403), Set(778, 775, 762, 759)),
-    779  -> Seq(Set(779, 776, 771, 769)),
-    780  -> Seq(Set(780, 775, 772, 764)),
-    781  -> Seq(Set(781, 779, 765, 764)),
-    782  -> Seq(Set(782, 453), Set(782, 780, 779, 773)),
-    783  -> Seq(Set(783, 715), Set(783, 782, 776, 773)),
-    784  -> Seq(Set(784, 778, 775, 771)),
-    785  -> Seq(Set(785, 693), Set(785, 780, 776, 775)),
-    786  -> Seq(Set(786, 782, 780, 771)),
+    395 -> Seq(Set(395, 390, 389, 384)),
+    396 -> Seq(Set(396, 371), Set(396, 392, 390, 389)),
+    397 -> Seq(Set(397, 392, 387, 385)),
+    398 -> Seq(Set(398, 393, 392, 384)),
+    399 -> Seq(Set(399, 313), Set(399, 397, 390, 388)),
+    400 -> Seq(Set(400, 398, 397, 395)),
+    401 -> Seq(Set(401, 249), Set(401, 399, 392, 389)),
+    402 -> Seq(Set(402, 399, 398, 393)),
+    403 -> Seq(Set(403, 398, 395, 394)),
+    404 -> Seq(Set(404, 215), Set(404, 400, 398, 397)),
+    405 -> Seq(Set(405, 398, 397, 388)),
+    406 -> Seq(Set(406, 249), Set(406, 402, 397, 393)),
+    407 -> Seq(Set(407, 336), Set(407, 402, 400, 398)),
+    408 -> Seq(Set(408, 407, 403, 401)),
+    409 -> Seq(Set(409, 322), Set(409, 406, 404, 402)),
+    410 -> Seq(Set(410, 407, 406, 400)),
+    411 -> Seq(Set(411, 408, 401, 399)),
+    412 -> Seq(Set(412, 265), Set(412, 409, 404, 401)),
+    413 -> Seq(Set(413, 407, 406, 403)),
+    414 -> Seq(Set(414, 405, 401, 398)),
+    415 -> Seq(Set(415, 313), Set(415, 413, 411, 406)),
+    416 -> Seq(Set(416, 414, 411, 407)),
+    417 -> Seq(Set(417, 310), Set(417, 416, 414, 407)),
+    418 -> Seq(Set(418, 417, 415, 403)),
+    419 -> Seq(Set(419, 415, 414, 404)),
+    420 -> Seq(Set(420, 412, 410, 407)),
+    421 -> Seq(Set(421, 419, 417, 416)),
+    422 -> Seq(Set(422, 273), Set(422, 421, 416, 412)),
+    423 -> Seq(Set(423, 398), Set(423, 420, 418, 414)),
+    424 -> Seq(Set(424, 422, 417, 415)),
+    425 -> Seq(Set(425, 413), Set(425, 422, 421, 418)),
+    426 -> Seq(Set(426, 415, 414, 412)),
+    427 -> Seq(Set(427, 422, 421, 416)),
+    428 -> Seq(Set(428, 323), Set(428, 426, 425, 417)),
+    429 -> Seq(Set(429, 422, 421, 419)),
+    430 -> Seq(Set(430, 419, 417, 415)),
+    431 -> Seq(Set(431, 311), Set(431, 430, 428, 426)),
+    432 -> Seq(Set(432, 429, 428, 419)),
+    433 -> Seq(Set(433, 400), Set(433, 430, 428, 422)),
+    434 -> Seq(Set(434, 429, 423, 422)),
+    435 -> Seq(Set(435, 430, 426, 423)),
+    436 -> Seq(Set(436, 271), Set(436, 432, 431, 430)),
+    437 -> Seq(Set(437, 436, 435, 431)),
+    438 -> Seq(Set(438, 373), Set(438, 436, 432, 421)),
+    439 -> Seq(Set(439, 390), Set(439, 437, 436, 431)),
+    440 -> Seq(Set(440, 439, 437, 436)),
+    441 -> Seq(Set(441, 410), Set(441, 440, 433, 430)),
+    442 -> Seq(Set(442, 440, 437, 435)),
+    443 -> Seq(Set(443, 442, 437, 433)),
+    444 -> Seq(Set(444, 435, 432, 431)),
+    445 -> Seq(Set(445, 441, 439, 438)),
+    446 -> Seq(Set(446, 341), Set(446, 442, 439, 431)),
+    447 -> Seq(Set(447, 374), Set(447, 446, 441, 438)),
+    448 -> Seq(Set(448, 444, 442, 437)),
+    449 -> Seq(Set(449, 315), Set(449, 446, 440, 438)),
+    450 -> Seq(Set(450, 371), Set(450, 443, 438, 434)),
+    451 -> Seq(Set(451, 450, 441, 435)),
+    452 -> Seq(Set(452, 448, 447, 446)),
+    453 -> Seq(Set(453, 449, 447, 438)),
+    454 -> Seq(Set(454, 449, 445, 444)),
+    455 -> Seq(Set(455, 417), Set(455, 453, 449, 444)),
+    456 -> Seq(Set(456, 454, 445, 433)),
+    457 -> Seq(Set(457, 441), Set(457, 454, 449, 446)),
+    458 -> Seq(Set(458, 255), Set(458, 453, 448, 445)),
+    459 -> Seq(Set(459, 457, 454, 447)),
+    460 -> Seq(Set(460, 399), Set(460, 459, 455, 451)),
+    461 -> Seq(Set(461, 460, 455, 454)),
+    462 -> Seq(Set(462, 389), Set(462, 457, 451, 450)),
+    463 -> Seq(Set(463, 370), Set(463, 456, 455, 452)),
+    464 -> Seq(Set(464, 460, 455, 441)),
+    465 -> Seq(Set(465, 406), Set(465, 463, 462, 457)),
+    466 -> Seq(Set(466, 460, 455, 452)),
+    467 -> Seq(Set(467, 466, 461, 456)),
+    468 -> Seq(Set(468, 464, 459, 453)),
+    469 -> Seq(Set(469, 467, 464, 460)),
+    470 -> Seq(Set(470, 321), Set(470, 468, 462, 461)),
+    471 -> Seq(Set(471, 470), Set(471, 469, 468, 465)),
+    472 -> Seq(Set(472, 470, 469, 461)),
+    473 -> Seq(Set(473, 470, 467, 465)),
+    474 -> Seq(Set(474, 283), Set(474, 465, 463, 456)),
+    475 -> Seq(Set(475, 471, 467, 466)),
+    476 -> Seq(Set(476, 461), Set(476, 475, 468, 466)),
+    477 -> Seq(Set(477, 470, 462, 461)),
+    478 -> Seq(Set(478, 357), Set(478, 477, 474, 472)),
+    479 -> Seq(Set(479, 375), Set(479, 475, 472, 470)),
+    480 -> Seq(Set(480, 473, 467, 464)),
+    481 -> Seq(Set(481, 343), Set(481, 480, 472, 471)),
+    482 -> Seq(Set(482, 477, 476, 473)),
+    483 -> Seq(Set(483, 479, 477, 474)),
+    484 -> Seq(Set(484, 379), Set(484, 483, 482, 470)),
+    485 -> Seq(Set(485, 479, 469, 468)),
+    486 -> Seq(Set(486, 481, 478, 472)),
+    487 -> Seq(Set(487, 393), Set(487, 485, 483, 478)),
+    488 -> Seq(Set(488, 487, 485, 484)),
+    489 -> Seq(Set(489, 406), Set(489, 484, 483, 480)),
+    490 -> Seq(Set(490, 271), Set(490, 485, 483, 481)),
+    491 -> Seq(Set(491, 488, 485, 480)),
+    492 -> Seq(Set(492, 491, 485, 484)),
+    493 -> Seq(Set(493, 490, 488, 483)),
+    494 -> Seq(Set(494, 357), Set(494, 493, 489, 481)),
+    495 -> Seq(Set(495, 419), Set(495, 494, 486, 480)),
+    496 -> Seq(Set(496, 494, 491, 480)),
+    497 -> Seq(Set(497, 419), Set(497, 493, 488, 486)),
+    498 -> Seq(Set(498, 495, 489, 487)),
+    499 -> Seq(Set(499, 494, 493, 488)),
+    500 -> Seq(Set(500, 499, 494, 490)),
+    501 -> Seq(Set(501, 499, 497, 496)),
+    502 -> Seq(Set(502, 498, 497, 494)),
+    503 -> Seq(Set(503, 500), Set(503, 502, 501, 500)),
+    504 -> Seq(Set(504, 502, 490, 483)),
+    505 -> Seq(Set(505, 349), Set(505, 500, 497, 493)),
+    506 -> Seq(Set(506, 411), Set(506, 501, 494, 491)),
+    507 -> Seq(Set(507, 504, 501, 494)),
+    508 -> Seq(Set(508, 399), Set(508, 505, 500, 495)),
+    509 -> Seq(Set(509, 506, 502, 501)),
+    510 -> Seq(Set(510, 501, 500, 498)),
+    511 -> Seq(Set(511, 501), Set(511, 509, 503, 501)),
+    512 -> Seq(Set(512, 510, 507, 504)),
+    513 -> Seq(Set(513, 428), Set(513, 505, 503, 500)),
+    514 -> Seq(Set(514, 511, 509, 507)),
+    515 -> Seq(Set(515, 511, 508, 501)),
+    516 -> Seq(Set(516, 514, 511, 509)),
+    517 -> Seq(Set(517, 515, 507, 505)),
+    518 -> Seq(Set(518, 485), Set(518, 516, 515, 507)),
+    519 -> Seq(Set(519, 440), Set(519, 517, 511, 507)),
+    520 -> Seq(Set(520, 509, 507, 503)),
+    521 -> Seq(Set(521, 489), Set(521, 519, 514, 512)),
+    522 -> Seq(Set(522, 518, 509, 507)),
+    523 -> Seq(Set(523, 521, 517, 510)),
+    524 -> Seq(Set(524, 357), Set(524, 523, 519, 515)),
+    525 -> Seq(Set(525, 524, 521, 519)),
+    526 -> Seq(Set(526, 525, 521, 517)),
+    527 -> Seq(Set(527, 480), Set(527, 526, 520, 518)),
+    528 -> Seq(Set(528, 526, 522, 517)),
+    529 -> Seq(Set(529, 487), Set(529, 528, 525, 522)),
+    530 -> Seq(Set(530, 527, 523, 520)),
+    531 -> Seq(Set(531, 529, 525, 519)),
+    532 -> Seq(Set(532, 531), Set(532, 529, 528, 522)),
+    533 -> Seq(Set(533, 531, 530, 529)),
+    534 -> Seq(Set(534, 533, 529, 527)),
+    535 -> Seq(Set(535, 533, 529, 527)),
+    536 -> Seq(Set(536, 533, 531, 529)),
+    537 -> Seq(Set(537, 443), Set(537, 536, 535, 527)),
+    538 -> Seq(Set(538, 537, 536, 533)),
+    539 -> Seq(Set(539, 535, 534, 529)),
+    540 -> Seq(Set(540, 361), Set(540, 537, 534, 529)),
+    541 -> Seq(Set(541, 537, 531, 528)),
+    542 -> Seq(Set(542, 540, 539, 533)),
+    543 -> Seq(Set(543, 527), Set(543, 538, 536, 532)),
+    544 -> Seq(Set(544, 538, 535, 531)),
+    545 -> Seq(Set(545, 423), Set(545, 539, 537, 532)),
+    546 -> Seq(Set(546, 545, 544, 538)),
+    547 -> Seq(Set(547, 543, 540, 534)),
+    548 -> Seq(Set(548, 545, 543, 538)),
+    549 -> Seq(Set(549, 546, 545, 533)),
+    550 -> Seq(Set(550, 357), Set(550, 546, 533, 529)),
+    551 -> Seq(Set(551, 416), Set(551, 550, 547, 542)),
+    552 -> Seq(Set(552, 550, 547, 532)),
+    553 -> Seq(Set(553, 514), Set(553, 550, 549, 542)),
+    554 -> Seq(Set(554, 551, 546, 543)),
+    555 -> Seq(Set(555, 551, 546, 545)),
+    556 -> Seq(Set(556, 403), Set(556, 549, 546, 540)),
+    557 -> Seq(Set(557, 552, 551, 550)),
+    558 -> Seq(Set(558, 553, 549, 544)),
+    559 -> Seq(Set(559, 525), Set(559, 557, 552, 550)),
+    560 -> Seq(Set(560, 554, 551, 549)),
+    561 -> Seq(Set(561, 490), Set(561, 558, 552, 550)),
+    562 -> Seq(Set(562, 560, 558, 551)),
+    563 -> Seq(Set(563, 561, 554, 549)),
+    564 -> Seq(Set(564, 401), Set(564, 563, 561, 558)),
+    565 -> Seq(Set(565, 564, 559, 554)),
+    566 -> Seq(Set(566, 413), Set(566, 564, 561, 560)),
+    567 -> Seq(Set(567, 424), Set(567, 563, 557, 556)),
+    568 -> Seq(Set(568, 558, 557, 551)),
+    569 -> Seq(Set(569, 492), Set(569, 568, 559, 557)),
+    570 -> Seq(Set(570, 503), Set(570, 563, 558, 552)),
+    571 -> Seq(Set(571, 569, 566, 561)),
+    572 -> Seq(Set(572, 571, 564, 560)),
+    573 -> Seq(Set(573, 569, 567, 563)),
+    574 -> Seq(Set(574, 561), Set(574, 569, 565, 560)),
+    575 -> Seq(Set(575, 429), Set(575, 572, 570, 569)),
+    576 -> Seq(Set(576, 573, 572, 563)),
+    577 -> Seq(Set(577, 552), Set(577, 575, 574, 569)),
+    578 -> Seq(Set(578, 562, 556, 555)),
+    579 -> Seq(Set(579, 572, 570, 567)),
+    580 -> Seq(Set(580, 579, 576, 574)),
+    581 -> Seq(Set(581, 575, 574, 568)),
+    582 -> Seq(Set(582, 497), Set(582, 579, 576, 571)),
+    583 -> Seq(Set(583, 453), Set(583, 581, 577, 575)),
+    584 -> Seq(Set(584, 581, 571, 570)),
+    585 -> Seq(Set(585, 464), Set(585, 583, 582, 577)),
+    586 -> Seq(Set(586, 584, 581, 579)),
+    587 -> Seq(Set(587, 586, 581, 576)),
+    588 -> Seq(Set(588, 437), Set(588, 577, 572, 571)),
+    589 -> Seq(Set(589, 586, 585, 579)),
+    590 -> Seq(Set(590, 497), Set(590, 588, 587, 578)),
+    591 -> Seq(Set(591, 587, 585, 582)),
+    592 -> Seq(Set(592, 591, 573, 568)),
+    593 -> Seq(Set(593, 507), Set(593, 588, 585, 584)),
+    594 -> Seq(Set(594, 575), Set(594, 586, 584, 583)),
+    595 -> Seq(Set(595, 594, 593, 586)),
+    596 -> Seq(Set(596, 592, 591, 590)),
+    597 -> Seq(Set(597, 588, 585, 583)),
+    598 -> Seq(Set(598, 597, 592, 591)),
+    599 -> Seq(Set(599, 569), Set(599, 593, 591, 590)),
+    600 -> Seq(Set(600, 599, 590, 589)),
+    601 -> Seq(Set(601, 400), Set(601, 600, 597, 589)),
+    602 -> Seq(Set(602, 596, 594, 591)),
+    603 -> Seq(Set(603, 600, 599, 597)),
+    604 -> Seq(Set(604, 600, 598, 589)),
+    605 -> Seq(Set(605, 600, 598, 595)),
+    606 -> Seq(Set(606, 602, 599, 591)),
+    607 -> Seq(Set(607, 502), Set(607, 600, 598, 595)),
+    608 -> Seq(Set(608, 606, 602, 585)),
+    609 -> Seq(Set(609, 578), Set(609, 601, 600, 597)),
+    610 -> Seq(Set(610, 483), Set(610, 602, 600, 599)),
+    611 -> Seq(Set(611, 609, 607, 601)),
+    612 -> Seq(Set(612, 607, 602, 598)),
+    613 -> Seq(Set(613, 609, 603, 594)),
+    614 -> Seq(Set(614, 613, 612, 607)),
+    615 -> Seq(Set(615, 404), Set(615, 614, 609, 608)),
+    616 -> Seq(Set(616, 614, 602, 597)),
+    617 -> Seq(Set(617, 417), Set(617, 612, 608, 607)),
+    618 -> Seq(Set(618, 615, 604, 598)),
+    619 -> Seq(Set(619, 614, 611, 610)),
+    620 -> Seq(Set(620, 619, 618, 611)),
+    621 -> Seq(Set(621, 616, 615, 609)),
+    622 -> Seq(Set(622, 325), Set(622, 612, 610, 605)),
+    623 -> Seq(Set(623, 555), Set(623, 614, 613, 612)),
+    624 -> Seq(Set(624, 617, 615, 612)),
+    625 -> Seq(Set(625, 492), Set(625, 620, 617, 613)),
+    626 -> Seq(Set(626, 623, 621, 613)),
+    627 -> Seq(Set(627, 622, 617, 613)),
+    628 -> Seq(Set(628, 405), Set(628, 626, 617, 616)),
+    629 -> Seq(Set(629, 627, 624, 623)),
+    630 -> Seq(Set(630, 628, 626, 623)),
+    631 -> Seq(Set(631, 324), Set(631, 625, 623, 617)),
+    632 -> Seq(Set(632, 629, 619, 613)),
+    633 -> Seq(Set(633, 532), Set(633, 632, 631, 626)),
+    634 -> Seq(Set(634, 319), Set(634, 631, 629, 627)),
+    635 -> Seq(Set(635, 631, 625, 621)),
+    636 -> Seq(Set(636, 632, 628, 623)),
+    637 -> Seq(Set(637, 636, 628, 623)),
+    638 -> Seq(Set(638, 637, 633, 632)),
+    639 -> Seq(Set(639, 623), Set(639, 636, 635, 629)),
+    640 -> Seq(Set(640, 638, 637, 626)),
+    641 -> Seq(Set(641, 630), Set(641, 640, 636, 622)),
+    642 -> Seq(Set(642, 523), Set(642, 636, 633, 632)),
+    643 -> Seq(Set(643, 641, 640, 632)),
+    644 -> Seq(Set(644, 634, 633, 632)),
+    645 -> Seq(Set(645, 641, 637, 634)),
+    646 -> Seq(Set(646, 397), Set(646, 635, 634, 633)),
+    647 -> Seq(Set(647, 642), Set(647, 646, 643, 642)),
+    648 -> Seq(Set(648, 647, 626, 625)),
+    649 -> Seq(Set(649, 612), Set(649, 648, 644, 638)),
+    650 -> Seq(Set(650, 647), Set(650, 644, 635, 632)),
+    651 -> Seq(Set(651, 646, 638, 637)),
+    652 -> Seq(Set(652, 559), Set(652, 647, 643, 641)),
+    653 -> Seq(Set(653, 646, 645, 643)),
+    654 -> Seq(Set(654, 649, 643, 640)),
+    655 -> Seq(Set(655, 567), Set(655, 653, 639, 638)),
+    656 -> Seq(Set(656, 646, 638, 637)),
+    657 -> Seq(Set(657, 619), Set(657, 656, 650, 649)),
+    658 -> Seq(Set(658, 603), Set(658, 651, 648, 646)),
+    659 -> Seq(Set(659, 657, 655, 644)),
+    660 -> Seq(Set(660, 657, 656, 648)),
+    661 -> Seq(Set(661, 657, 650, 649)),
+    662 -> Seq(Set(662, 365), Set(662, 659, 656, 650)),
+    663 -> Seq(Set(663, 406), Set(663, 655, 652, 649)),
+    664 -> Seq(Set(664, 662, 660, 649)),
+    665 -> Seq(Set(665, 632), Set(665, 661, 659, 654)),
+    666 -> Seq(Set(666, 664, 659, 656)),
+    667 -> Seq(Set(667, 664, 660, 649)),
+    668 -> Seq(Set(668, 658, 656, 651)),
+    669 -> Seq(Set(669, 667, 665, 664)),
+    670 -> Seq(Set(670, 517), Set(670, 669, 665, 664)),
+    671 -> Seq(Set(671, 656), Set(671, 669, 665, 662)),
+    672 -> Seq(Set(672, 667, 666, 661)),
+    673 -> Seq(Set(673, 645), Set(673, 666, 664, 663)),
+    674 -> Seq(Set(674, 671, 665, 660)),
+    675 -> Seq(Set(675, 674, 672, 669)),
+    676 -> Seq(Set(676, 435), Set(676, 675, 671, 664)),
+    677 -> Seq(Set(677, 674, 673, 669)),
+    678 -> Seq(Set(678, 675, 673, 663)),
+    679 -> Seq(Set(679, 613), Set(679, 676, 667, 661)),
+    680 -> Seq(Set(680, 679, 650, 645)),
+    681 -> Seq(Set(681, 678, 672, 670)),
+    682 -> Seq(Set(682, 681, 679, 675)),
+    683 -> Seq(Set(683, 682, 677, 672)),
+    684 -> Seq(Set(684, 681, 671, 666)),
+    685 -> Seq(Set(685, 684, 682, 681)),
+    686 -> Seq(Set(686, 489), Set(686, 684, 674, 673)),
+    687 -> Seq(Set(687, 674), Set(687, 682, 675, 673)),
+    688 -> Seq(Set(688, 682, 674, 669)),
+    689 -> Seq(Set(689, 675), Set(689, 686, 683, 681)),
+    690 -> Seq(Set(690, 687, 683, 680)),
+    691 -> Seq(Set(691, 689, 685, 678)),
+    692 -> Seq(Set(692, 393), Set(692, 687, 686, 678)),
+    693 -> Seq(Set(693, 691, 685, 678)),
+    694 -> Seq(Set(694, 691, 681, 677)),
+    695 -> Seq(Set(695, 483), Set(695, 694, 691, 686)),
+    696 -> Seq(Set(696, 694, 686, 673)),
+    697 -> Seq(Set(697, 430), Set(697, 689, 685, 681)),
+    698 -> Seq(Set(698, 483), Set(698, 690, 689, 688)),
+    699 -> Seq(Set(699, 698, 689, 684)),
+    700 -> Seq(Set(700, 698, 695, 694)),
+    701 -> Seq(Set(701, 699, 697, 685)),
+    702 -> Seq(Set(702, 665), Set(702, 701, 699, 695)),
+    703 -> Seq(Set(703, 702, 696, 691)),
+    704 -> Seq(Set(704, 701, 699, 692)),
+    705 -> Seq(Set(705, 686), Set(705, 704, 698, 697)),
+    706 -> Seq(Set(706, 697, 695, 692)),
+    707 -> Seq(Set(707, 702, 699, 692)),
+    708 -> Seq(Set(708, 421), Set(708, 706, 704, 703)),
+    709 -> Seq(Set(709, 708, 706, 705)),
+    710 -> Seq(Set(710, 709, 696, 695)),
+    711 -> Seq(Set(711, 619), Set(711, 704, 703, 700)),
+    712 -> Seq(Set(712, 709, 708, 707)),
+    713 -> Seq(Set(713, 672), Set(713, 706, 703, 696)),
+    714 -> Seq(Set(714, 691), Set(714, 709, 707, 701)),
+    715 -> Seq(Set(715, 714, 711, 708)),
+    716 -> Seq(Set(716, 533), Set(716, 706, 705, 704)),
+    717 -> Seq(Set(717, 716, 710, 701)),
+    718 -> Seq(Set(718, 717, 716, 713)),
+    719 -> Seq(Set(719, 569), Set(719, 711, 710, 707)),
+    720 -> Seq(Set(720, 718, 712, 709)),
+    721 -> Seq(Set(721, 712), Set(721, 720, 713, 712)),
+    722 -> Seq(Set(722, 491), Set(722, 721, 718, 707)),
+    723 -> Seq(Set(723, 717, 710, 707)),
+    724 -> Seq(Set(724, 719, 716, 711)),
+    725 -> Seq(Set(725, 720, 719, 716), Set(758)),
+    726 -> Seq(Set(726, 721), Set(726, 725, 722, 721)),
+    727 -> Seq(Set(727, 547), Set(727, 721, 719, 716)),
+    728 -> Seq(Set(728, 726, 725, 724), Set(761)),
+    729 -> Seq(Set(729, 671), Set(729, 726, 724, 718)),
+    730 -> Seq(Set(730, 583), Set(730, 726, 715, 711)),
+    731 -> Seq(Set(731, 729, 725, 723), Set(764)),
+    732 -> Seq(Set(732, 729, 728, 725), Set(765)),
+    733 -> Seq(Set(733, 731, 726, 725), Set(766)),
+    734 -> Seq(Set(734, 724, 721, 720), Set(767)),
+    735 -> Seq(Set(735, 691), Set(735, 733, 728, 727)),
+    736 -> Seq(Set(736, 730, 728, 723), Set(769)),
+    737 -> Seq(Set(737, 732), Set(737, 736, 733, 732)),
+    738 -> Seq(Set(738, 391), Set(738, 730, 729, 727)),
+    739 -> Seq(Set(739, 731, 723, 721), Set(772)),
+    740 -> Seq(Set(740, 587), Set(740, 737, 728, 716)),
+    741 -> Seq(Set(741, 738, 733, 732), Set(774)),
+    742 -> Seq(Set(742, 741, 738, 730), Set(775)),
+    743 -> Seq(Set(743, 653), Set(743, 742, 731, 730)),
+    744 -> Seq(Set(744, 743, 733, 731), Set(777)),
+    745 -> Seq(Set(745, 487), Set(745, 740, 738, 737)),
+    746 -> Seq(Set(746, 395), Set(746, 738, 733, 728)),
+    747 -> Seq(Set(747, 743, 741, 737), Set(780)),
+    748 -> Seq(Set(748, 744, 743, 733), Set(781)),
+    749 -> Seq(Set(749, 748, 743, 742), Set(782)),
+    750 -> Seq(Set(750, 746, 741, 734), Set(783)),
+    751 -> Seq(Set(751, 733), Set(751, 750, 748, 740)),
+    752 -> Seq(Set(752, 749, 732, 731), Set(785)),
+    753 -> Seq(Set(753, 595), Set(753, 748, 745, 740)),
+    754 -> Seq(Set(754, 735), Set(754, 742, 740, 735)),
+    755 -> Seq(Set(755, 754, 745, 743), Set(2048)),
+    756 -> Seq(Set(756, 407), Set(756, 755, 747, 740)),
+    757 -> Seq(Set(757, 756, 751, 750)),
+    758 -> Seq(Set(758, 757, 746, 741)),
+    759 -> Seq(Set(759, 661), Set(759, 757, 756, 750)),
+    760 -> Seq(Set(760, 757, 747, 734)),
+    761 -> Seq(Set(761, 758), Set(761, 760, 759, 758)),
+    762 -> Seq(Set(762, 679), Set(762, 761, 755, 745)),
+    763 -> Seq(Set(763, 754, 749, 747)),
+    764 -> Seq(Set(764, 761, 759, 758)),
+    765 -> Seq(Set(765, 760, 755, 754)),
+    766 -> Seq(Set(766, 757, 747, 744)),
+    767 -> Seq(Set(767, 599), Set(767, 763, 760, 759)),
+    768 -> Seq(Set(768, 764, 751, 749)),
+    769 -> Seq(Set(769, 649), Set(769, 763, 762, 760)),
+    770 -> Seq(Set(770, 768, 765, 756)),
+    771 -> Seq(Set(771, 765, 756, 754)),
+    772 -> Seq(Set(772, 765), Set(772, 767, 766, 764)),
+    773 -> Seq(Set(773, 767, 765, 763)),
+    774 -> Seq(Set(774, 589), Set(774, 767, 760, 758)),
+    775 -> Seq(Set(775, 408), Set(775, 771, 769, 768)),
+    776 -> Seq(Set(776, 773, 764, 759)),
+    777 -> Seq(Set(777, 748), Set(777, 776, 767, 761)),
+    778 -> Seq(Set(778, 403), Set(778, 775, 762, 759)),
+    779 -> Seq(Set(779, 776, 771, 769)),
+    780 -> Seq(Set(780, 775, 772, 764)),
+    781 -> Seq(Set(781, 779, 765, 764)),
+    782 -> Seq(Set(782, 453), Set(782, 780, 779, 773)),
+    783 -> Seq(Set(783, 715), Set(783, 782, 776, 773)),
+    784 -> Seq(Set(784, 778, 775, 771)),
+    785 -> Seq(Set(785, 693), Set(785, 780, 776, 775)),
+    786 -> Seq(Set(786, 782, 780, 771)),
     1024 -> Seq(Set(1024, 1015, 1002, 1001)),
     2048 -> Seq(Set(2048, 2035, 2034, 2029)),
-    4096 -> Seq(Set(4096, 4095, 4081, 4069)) )
+    4096 -> Seq(Set(4096, 4095, 4081, 4069))
+  )
 
 }
diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala
index 3a44385a..2566c8d6 100644
--- a/src/main/scala/chisel3/util/random/PRNG.scala
+++ b/src/main/scala/chisel3/util/random/PRNG.scala
@@ -11,17 +11,17 @@ import chisel3.util.Valid
   */
 class PRNGIO(val n: Int) extends Bundle {
 
-  /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) 
+  /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state)
     * @group Signals
     */
   val seed: Valid[Vec[Bool]] = Input(Valid(Vec(n, Bool())))
 
-  /** When asserted, the PRNG will increment by one 
+  /** When asserted, the PRNG will increment by one
     * @group Signals
     */
   val increment: Bool = Input(Bool())
 
-  /** The current state of the PRNG 
+  /** The current state of the PRNG
     * @group Signals
     */
   val out: Vec[Bool] = Output(Vec(n, Bool()))
@@ -34,7 +34,8 @@ class PRNGIO(val n: Int) extends Bundle {
   * @param updateSeed if true, when loading the seed the state will be updated as if the seed were the current state, if
   * false, the state will be set to the seed
   */
-abstract class PRNG(val width: Int, val seed: Option[BigInt], step: Int = 1, updateSeed: Boolean = false) extends Module {
+abstract class PRNG(val width: Int, val seed: Option[BigInt], step: Int = 1, updateSeed: Boolean = false)
+    extends Module {
   require(width > 0, s"Width must be greater than zero! (Found '$width')")
   require(step > 0, s"Step size must be greater than one! (Found '$step')")
 
@@ -51,7 +52,7 @@ abstract class PRNG(val width: Int, val seed: Option[BigInt], step: Int = 1, upd
     * the PRNG state should be manually reset to a safe value. [[LFSR]] handles this by, based on the chosen reduction
     * operator, either sets or resets the least significant bit of the state.
     */
-  private [random] val state: Vec[Bool] = RegInit(resetValue)
+  private[random] val state: Vec[Bool] = RegInit(resetValue)
 
   /** State update function
     * @param s input state
@@ -63,14 +64,15 @@ abstract class PRNG(val width: Int, val seed: Option[BigInt], step: Int = 1, upd
     * @param s input state
     * @return the next state after `step` applications of [[PRNG.delta]]
     */
-  final def nextState(s: Seq[Bool]): Seq[Bool] = (0 until step).foldLeft(s){ case (s, _) => delta(s) }
+  final def nextState(s: Seq[Bool]): Seq[Bool] = (0 until step).foldLeft(s) { case (s, _) => delta(s) }
 
-  when (io.increment) {
+  when(io.increment) {
     state := nextState(state)
   }
 
-  when (io.seed.fire) {
-    state := (if (updateSeed) { nextState(io.seed.bits) } else { io.seed.bits })
+  when(io.seed.fire) {
+    state := (if (updateSeed) { nextState(io.seed.bits) }
+              else { io.seed.bits })
   }
 
   io.out := state
diff --git a/src/main/scala/chisel3/verilog.scala b/src/main/scala/chisel3/verilog.scala
index a91444de..b926a15c 100644
--- a/src/main/scala/chisel3/verilog.scala
+++ b/src/main/scala/chisel3/verilog.scala
@@ -8,8 +8,7 @@ object getVerilogString {
 }
 
 object emitVerilog {
-  def apply(gen: => RawModule, args: Array[String] = Array.empty,
-                  annotations: AnnotationSeq = Seq.empty): Unit = {
+  def apply(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): Unit = {
     (new ChiselStage).emitVerilog(gen, args, annotations)
   }
 }