1 files changed, 10 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 5d80502a..eeb2ab68 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -20,7 +20,8 @@ import chisel3._
   * @groupdesc Signals The actual hardware fields of the Bundle
   */
 class Valid[+T <: Data](gen: T) extends Bundle {
-  /** A bit that will be asserted when `bits` is valid 
+
+  /** A bit that will be asserted when `bits` is valid
     * @group Signals
     */
   val valid = Output(Bool())
@@ -28,14 +29,17 @@ class Valid[+T <: Data](gen: T) extends Bundle {
   /** The data to be transferred, qualified by `valid`
     * @group Signals
     */
-  val bits  = Output(gen)
+  val bits = Output(gen)
 
   /** True when `valid` is asserted
     * @return a Chisel [[Bool]] true if `valid` is asserted
     */
   def fire: Bool = valid
 
-  @deprecated("Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead", "Chisel 3.5")
+  @deprecated(
+    "Calling this function with an empty argument list is invalid in Scala 3. Use the form without parentheses instead",
+    "Chisel 3.5"
+  )
   def fire(dummy: Int = 0): Bool = valid
 }
 
@@ -122,7 +126,7 @@ object Pipe {
     } else {
       val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
-      val out = apply(v, b, latency-1)(compileOptions)
+      val out = apply(v, b, latency - 1)(compileOptions)
 
       TransitName.withSuffix("Pipe_valid")(out, v)
       TransitName.withSuffix("Pipe_bits")(out, b)
@@ -182,12 +186,12 @@ class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions:
     */
   class PipeIO extends Bundle {
 
-    /** [[Valid]] input 
+    /** [[Valid]] input
       * @group Signals
       */
     val enq = Input(Valid(gen))
 
-    /** [[Valid]] output. Data will appear here `latency` cycles after being valid at `enq`. 
+    /** [[Valid]] output. Data will appear here `latency` cycles after being valid at `enq`.
       * @group Signals
       */
     val deq = Output(Valid(gen))