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authorAditya Naik2024-06-03 19:41:04 -0700
committerAditya Naik2024-06-03 19:41:04 -0700
commit52824ce57e9d60fe6ef721cfb073249e654dcf46 (patch)
tree1763ea303391b0cf1c0e4e21e7b7d3626f4d64fb /src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
parenta529d0e962cbe6a8f32dcc87d5193df46c0ebc94 (diff)
fix stuff in src/
build is failing with a compile error in 3.3.3 due to something in Aggregate.scala. reduce to smallest form and file a bug report maybe?
Diffstat (limited to 'src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala')
-rw-r--r--src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index bd46abe9..15c6ff6f 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -4,6 +4,7 @@ package chisel3.util.experimental
import chisel3._
import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
import firrtl.annotations._
import firrtl.ir.{Module => _, _}
import firrtl.transforms.BlackBoxInlineAnno