fix stuff in src/

build is failing with a compile error in 3.3.3 due to something in
Aggregate.scala. reduce to smallest form and file a bug report maybe?

3 files changed, 4 insertions, 6 deletions

diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index bd46abe9..15c6ff6f 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -4,6 +4,7 @@ package chisel3.util.experimental
 
 import chisel3._
 import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.annotations._
 import firrtl.ir.{Module => _, _}
 import firrtl.transforms.BlackBoxInlineAnno
diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
index ce2da3c0..c5e9a5c3 100644
--- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
@@ -7,6 +7,7 @@ import chisel3.experimental.{annotate, ChiselAnnotation}
 import chisel3.util.{pla, BitPat}
 import chisel3.util.experimental.{getAnnotations, BitSet}
 import chisel3.internal.Builder
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.annotations.Annotation
 import logger.LazyLogging
 
diff --git a/src/main/scala/chisel3/util/experimental/group.scala b/src/main/scala/chisel3/util/experimental/group.scala
index 202c95d8..ac687da7 100644
--- a/src/main/scala/chisel3/util/experimental/group.scala
+++ b/src/main/scala/chisel3/util/experimental/group.scala
@@ -51,13 +51,9 @@ object group {
     newInstance:  String,
     outputSuffix: Option[String] = None,
     inputSuffix:  Option[String] = None
-  )(
-    implicit compileOptions: CompileOptions
   ): Unit = {
-    if (compileOptions.checkSynthesizable) {
-      components.foreach { data =>
-        requireIsHardware(data, s"Component ${data.toString} is marked to group, but is not bound.")
-      }
+    components.foreach { data =>
+      requireIsHardware(data, s"Component ${data.toString} is marked to group, but is not bound.")
     }
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = GroupAnnotation(components.map(_.toNamed), newModule, newInstance, outputSuffix, inputSuffix)