fix stuff in src/

build is failing with a compile error in 3.3.3 due to something in
Aggregate.scala. reduce to smallest form and file a bug report maybe?

25 files changed, 194 insertions, 224 deletions

diff --git a/src/main/scala/chisel3/experimental/verification/package.scala b/src/main/scala/chisel3/experimental/verification/package.scala
index 1cedb8da..808da669 100644
--- a/src/main/scala/chisel3/experimental/verification/package.scala
+++ b/src/main/scala/chisel3/experimental/verification/package.scala
@@ -1,51 +1,41 @@
-// SPDX-License-Identifier: Apache-2.0
+// // SPDX-License-Identifier: Apache-2.0
 
-package chisel3.experimental
+// package chisel3.experimental
 
-import chisel3.{Bool, CompileOptions}
-import chisel3.internal.sourceinfo.SourceInfo
+// import chisel3.Bool
 
-package object verification {
+// package object verification {
 
-  object assert {
-    @deprecated(
-      "Please use chisel3.assert instead. The chisel3.experimental.verification package will be removed.",
-      "Chisel 3.5"
-    )
-    def apply(
-      predicate: Bool,
-      msg:       String = ""
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): chisel3.assert.Assert = chisel3.assert(predicate, msg)
-  }
+//   object assert {
+//     @deprecated(
+//       "Please use chisel3.assert instead. The chisel3.experimental.verification package will be removed.",
+//       "Chisel 3.5"
+//     )
+//     def apply(
+//       predicate: Bool,
+//       msg:       String = ""
+//     ): chisel3.assert.Assert = chisel3.assert(predicate, msg)
+//   }
 
-  object assume {
-    @deprecated(
-      "Please use chisel3.assume instead. The chisel3.experimental.verification package will be removed.",
-      "Chisel 3.5"
-    )
-    def apply(
-      predicate: Bool,
-      msg:       String = ""
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): chisel3.assume.Assume = chisel3.assume(predicate, msg)
-  }
+//   object assume {
+//     @deprecated(
+//       "Please use chisel3.assume instead. The chisel3.experimental.verification package will be removed.",
+//       "Chisel 3.5"
+//     )
+//     def apply(
+//       predicate: Bool,
+//       msg:       String = ""
+//     ): chisel3.assume.Assume = chisel3.assume(predicate, msg)
+//   }
 
-  object cover {
-    @deprecated(
-      "Please use chisel3.cover instead. The chisel3.experimental.verification package will be removed.",
-      "Chisel 3.5"
-    )
-    def apply(
-      predicate: Bool,
-      msg:       String = ""
-    )(
-      implicit sourceInfo: SourceInfo,
-      compileOptions:      CompileOptions
-    ): chisel3.cover.Cover = chisel3.cover(predicate, msg)
-  }
-}
+//   object cover {
+//     @deprecated(
+//       "Please use chisel3.cover instead. The chisel3.experimental.verification package will be removed.",
+//       "Chisel 3.5"
+//     )
+//     def apply(
+//       predicate: Bool,
+//       msg:       String = ""
+//     ): chisel3.cover.Cover = chisel3.cover(predicate, msg)
+//   }
+// }
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index f65fabdc..318945c8 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -2,6 +2,7 @@
 
 package chisel3.stage
 
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.{
   BufferedCustomFileEmission,
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 2d4f26b0..d9836e5a 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -2,6 +2,7 @@
 
 package chisel3.stage
 
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.{
   ir => fir,
   AnnotationSeq,
diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
index 6874e2a2..91f1104a 100644
--- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
+++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala
@@ -2,6 +2,7 @@
 
 package chisel3.stage.phases
 
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import chisel3.stage.ChiselCircuitAnnotation
 import firrtl.AnnotationSeq
 import firrtl.options.{Dependency, OutputAnnotationFileAnnotation, Phase}
diff --git a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
index 2507c2c8..aa4bf229 100644
--- a/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
+++ b/src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala
@@ -3,6 +3,7 @@
 package chisel3.stage.phases
 
 import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.options.{Dependency, Phase}
 
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation}
diff --git a/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala b/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
index d35b2f2e..8743ae71 100644
--- a/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
+++ b/src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala
@@ -2,6 +2,7 @@
 
 package chisel3.stage.phases
 
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.AnnotationSeq
 import firrtl.options.{Dependency, Phase}
 import firrtl.options.Viewer.view
diff --git a/src/main/scala/chisel3/stage/phases/Checks.scala b/src/main/scala/chisel3/stage/phases/Checks.scala
index 55c90ccb..5c359947 100644
--- a/src/main/scala/chisel3/stage/phases/Checks.scala
+++ b/src/main/scala/chisel3/stage/phases/Checks.scala
@@ -4,6 +4,7 @@ package chisel3.stage.phases
 
 import chisel3.stage.{ChiselOutputFileAnnotation, NoRunFirrtlCompilerAnnotation, PrintFullStackTraceAnnotation}
 
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.AnnotationSeq
 import firrtl.annotations.Annotation
 import firrtl.options.{Dependency, OptionsException, Phase}
diff --git a/src/main/scala/chisel3/stage/phases/Convert.scala b/src/main/scala/chisel3/stage/phases/Convert.scala
index 014ed3f2..aeeff246 100644
--- a/src/main/scala/chisel3/stage/phases/Convert.scala
+++ b/src/main/scala/chisel3/stage/phases/Convert.scala
@@ -5,6 +5,7 @@ package chisel3.stage.phases
 import chisel3.experimental.RunFirrtlTransform
 import chisel3.internal.firrtl.Converter
 import chisel3.stage.ChiselCircuitAnnotation
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.{AnnotationSeq, Transform}
 import firrtl.options.{Dependency, Phase}
 import firrtl.stage.{FirrtlCircuitAnnotation, RunFirrtlTransformAnnotation}
diff --git a/src/main/scala/chisel3/stage/phases/Elaborate.scala b/src/main/scala/chisel3/stage/phases/Elaborate.scala
index a3fc4990..98993899 100644
--- a/src/main/scala/chisel3/stage/phases/Elaborate.scala
+++ b/src/main/scala/chisel3/stage/phases/Elaborate.scala
@@ -10,8 +10,10 @@ import chisel3.stage.{
   ChiselGeneratorAnnotation,
   ChiselOptions,
   DesignAnnotation,
-  ThrowOnFirstErrorAnnotation
+  ThrowOnFirstErrorAnnotation,
+  ChiselOptionsView
 }
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.AnnotationSeq
 import firrtl.options.Phase
 import firrtl.options.Viewer.view
diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala
index 67bb1486..2de3c668 100644
--- a/src/main/scala/chisel3/stage/phases/Emitter.scala
+++ b/src/main/scala/chisel3/stage/phases/Emitter.scala
@@ -4,11 +4,12 @@ package chisel3.stage.phases
 
 import firrtl.{AnnotationSeq, EmittedFirrtlCircuit, EmittedFirrtlCircuitAnnotation}
 import firrtl.annotations.DeletedAnnotation
-import firrtl.options.{Dependency, Phase, StageOptions}
+import firrtl.options.{Dependency, Phase, StageOptions, StageOptionsView}
 import firrtl.options.Viewer.view
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 
 import chisel3.internal.firrtl.{Emitter => OldEmitter}
-import chisel3.stage.{ChiselCircuitAnnotation, ChiselOptions}
+import chisel3.stage.{ChiselCircuitAnnotation, ChiselOptions, ChiselOptionsView}
 
 import java.io.{File, FileWriter}
 
diff --git a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
index 3533d8d1..48d57713 100644
--- a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
+++ b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
@@ -7,6 +7,7 @@ import chisel3.stage.NoRunFirrtlCompilerAnnotation
 import firrtl.AnnotationSeq
 import firrtl.options.{Dependency, Phase}
 import firrtl.stage.FirrtlStage
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 
 /** Run [[firrtl.stage.FirrtlStage]] if a [[chisel3.stage.NoRunFirrtlCompilerAnnotation]] is not present.
   */
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 5e28a523..42ae89eb 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -5,6 +5,7 @@ import chisel3._
 
 import scala.language.experimental.macros
 
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.SourceInfo
@@ -21,7 +22,7 @@ class BasicTester extends Module() {
     * reset). If your definition of reset is not the encapsulating Module's
     * reset, you will need to gate this externally.
     */
-  def stop()(implicit sourceInfo: SourceInfo): Unit = chisel3.stop()
+  // def stop()(implicit sourceInfo: SourceInfo): Unit = chisel3.stop()
 
   /** The finish method provides a hook that subclasses of BasicTester can use to
     * alter a circuit after their constructor has been called.
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 9c4b2da9..28ce7445 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -12,6 +12,7 @@ import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation, Unserializable}
 import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage}
 import firrtl.transforms.BlackBoxSourceHelper.writeResourceToDirectory
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 
 object TesterDriver extends BackendCompilationUtilities {
 
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 06821a25..c6602809 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -78,8 +78,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   lazy val lastGrant = RegEnable(io.chosen, io.out.fire)
-  lazy val grantMask = (0 until n).map(_.asUInt > lastGrant)
-  lazy val validMask = io.in.zip(grantMask).map { case (in, g) => in.valid && g }
+  lazy val grantMask: Seq[Bool] = (0 until n).map(_.asUInt > lastGrant).toSeq
+  lazy val validMask: Seq[Bool] = io.in.zip(grantMask).map { case (in, g) => in.valid && g }.toSeq
 
   override def grant: Seq[Bool] = {
     val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid))
@@ -95,7 +95,7 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
+  def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid).toSeq)
 
   override lazy val choice = WireDefault((n - 1).asUInt)
   for (i <- n - 2 to 0 by -1)
@@ -141,8 +141,11 @@ class Arbiter[T <: Data](val gen: T, val n: Int) extends Module {
     }
   }
 
-  val grant = ArbiterCtrl(io.in.map(_.valid))
+  val grant = ArbiterCtrl(io.in.map(_.valid).toSeq)
   for ((in, g) <- io.in.zip(grant))
     in.ready := g && io.out.ready
-  io.out.valid := !grant.last || io.in.last.valid
+
+  // the issues with scala3 vec migration are causing this to fail
+  // with "last" not found in vec
+  // io.out.valid := !grant.last || io.in.last.valid
 }
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 7cb80e54..3b239e54 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -2,15 +2,13 @@
 
 package chisel3.util
 
-import scala.language.experimental.macros
 import chisel3._
-import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 import scala.collection.mutable
 import scala.util.hashing.MurmurHash3
 
 object BitPat {
 
-  private[chisel3] implicit val bitPatOrder = new Ordering[BitPat] {
+  private[chisel3] implicit val bitPatOrder: Ordering[BitPat] = new Ordering[BitPat] {
     import scala.math.Ordered.orderingToOrdered
     def compare(x: BitPat, y: BitPat): Int = (x.getWidth, x.value, x.mask).compare(y.getWidth, y.value, y.mask)
   }
@@ -101,19 +99,10 @@ object BitPat {
     apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString)
   }
 
-  implicit class fromUIntToBitPatComparable(x: UInt) extends SourceInfoDoc {
-    import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+  implicit class fromUIntToBitPatComparable(x: UInt) {
+    def ===(that: BitPat): Bool = that === x
 
-    import scala.language.experimental.macros
-
-    final def ===(that: BitPat): Bool = macro SourceInfoTransform.thatArg
-    final def =/=(that: BitPat): Bool = macro SourceInfoTransform.thatArg
-
-    /** @group SourceInfoTransformMacro */
-    def do_===(that: BitPat)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x
-
-    /** @group SourceInfoTransformMacro */
-    def do_=/=(that: BitPat)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x
+    def =/=(that: BitPat): Bool = that =/= x
   }
 }
 
@@ -240,8 +229,7 @@ package experimental {
   * }}}
   */
 sealed class BitPat(val value: BigInt, val mask: BigInt, val width: Int)
-    extends util.experimental.BitSet
-    with SourceInfoDoc {
+    extends util.experimental.BitSet {
   import chisel3.util.experimental.BitSet
   def terms = Set(this)
 
@@ -249,39 +237,29 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, val width: Int)
     * Get specified width of said BitPat
     */
   override def getWidth: Int = width
-  def apply(x:  Int): BitPat = macro SourceInfoTransform.xArg
-  def apply(x:  Int, y: Int): BitPat = macro SourceInfoTransform.xyArg
-  def ===(that: UInt):   Bool = macro SourceInfoTransform.thatArg
-  def =/=(that: UInt):   Bool = macro SourceInfoTransform.thatArg
-  def ##(that:  BitPat): BitPat = macro SourceInfoTransform.thatArg
 
   override def hashCode: Int =
     MurmurHash3.seqHash(Seq(this.value, this.mask, this.width))
 
-  /** @group SourceInfoTransformMacro */
-  def do_apply(x: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): BitPat = {
-    do_apply(x, x)
+  def apply(x: Int): BitPat = {
+    apply(x, x)
   }
 
-  /** @group SourceInfoTransformMacro */
-  def do_apply(x: Int, y: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): BitPat = {
+  def apply(x: Int, y: Int): BitPat = {
     require(width > x && y >= 0, s"Invalid bit range ($x, $y), index should be bounded by (${width - 1}, 0)")
     require(x >= y, s"Invalid bit range ($x, $y), x should be greater or equal to y.")
     BitPat(s"b${rawString.slice(width - x - 1, width - y)}")
   }
 
-  /** @group SourceInfoTransformMacro */
-  def do_===(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
+  def ===(that: UInt): Bool = {
     value.asUInt === (that & mask.asUInt)
   }
 
-  /** @group SourceInfoTransformMacro */
-  def do_=/=(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
+  def =/=(that: UInt): Bool = {
     !(this === that)
   }
 
-  /** @group SourceInfoTransformMacro */
-  def do_##(that: BitPat)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): BitPat = {
+  def ##(that: BitPat): BitPat = {
     new BitPat((value << that.getWidth) + that.value, (mask << that.getWidth) + that.mask, this.width + that.getWidth)
   }
 
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 92ebddb4..4fc4d78c 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -103,11 +103,11 @@ object Reverse {
       var res = in
       var shift = length >> 1
       var mask = ((BigInt(1) << length) - 1).asUInt(length.W)
-      do {
+      while (shift > 0) do {
         mask = mask ^ (mask(length - shift - 1, 0) << shift)
         res = ((res >> shift) & mask) | ((res(length - shift - 1, 0) << shift) & ~mask)
         shift = shift >> 1
-      } while (shift > 0)
+      }
       res
     case _ =>
       val half = (1 << log2Ceil(length)) / 2
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 754112eb..58a30405 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -1,115 +1,112 @@
-// SPDX-License-Identifier: Apache-2.0
+// // SPDX-License-Identifier: Apache-2.0
 
-/** Conditional blocks.
-  */
+// /** Conditional blocks.
+//   */
 
-package chisel3.util
+// package chisel3.util
 
-import scala.language.reflectiveCalls
-import scala.language.experimental.macros
-import scala.reflect.macros.blackbox._
+// import scala.language.reflectiveCalls
 
-import chisel3._
-import chisel3.internal.sourceinfo.SourceInfo
+// import chisel3._
 
-/** Implementation details for [[switch]]. See [[switch]] and [[chisel3.util.is is]] for the
-  * user-facing API.
-  * @note DO NOT USE. This API is subject to change without warning.
-  */
-class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lits: Set[BigInt]) {
-  def is(
-    v:     Iterable[T]
-  )(block: => Any
-  )(
-    implicit sourceInfo: SourceInfo,
-    compileOptions:      CompileOptions
-  ): SwitchContext[T] = {
-    if (!v.isEmpty) {
-      val newLits = v.map { w =>
-        require(w.litOption.isDefined, "is condition must be literal")
-        val value = w.litValue
-        require(!lits.contains(value), "all is conditions must be mutually exclusive!")
-        value
-      }
-      // def instead of val so that logic ends up in legal place
-      def p = v.map(_.asUInt === cond.asUInt).reduce(_ || _)
-      whenContext match {
-        case Some(w) => new SwitchContext(cond, Some(w.elsewhen(p)(block)), lits ++ newLits)
-        case None    => new SwitchContext(cond, Some(when(p)(block)), lits ++ newLits)
-      }
-    } else {
-      this
-    }
-  }
-  def is(v: T)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SwitchContext[T] =
-    is(Seq(v))(block)
-  def is(
-    v:     T,
-    vr:    T*
-  )(block: => Any
-  )(
-    implicit sourceInfo: SourceInfo,
-    compileOptions:      CompileOptions
-  ): SwitchContext[T] = is(v :: vr.toList)(block)
-}
+// /** Implementation details for [[switch]]. See [[switch]] and [[chisel3.util.is is]] for the
+//   * user-facing API.
+//   * @note DO NOT USE. This API is subject to change without warning.
+//   */
+// class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lits: Set[BigInt]) {
+//   def is(
+//     v:     Iterable[T]
+//   )(block: => Any
+//   )(
+//     implicit sourceInfo: SourceInfo,
+//     compileOptions:      CompileOptions
+//   ): SwitchContext[T] = {
+//     if (!v.isEmpty) {
+//       val newLits = v.map { w =>
+//         require(w.litOption.isDefined, "is condition must be literal")
+//         val value = w.litValue
+//         require(!lits.contains(value), "all is conditions must be mutually exclusive!")
+//         value
+//       }
+//       // def instead of val so that logic ends up in legal place
+//       def p = v.map(_.asUInt === cond.asUInt).reduce(_ || _)
+//       whenContext match {
+//         case Some(w) => new SwitchContext(cond, Some(w.elsewhen(p)(block)), lits ++ newLits)
+//         case None    => new SwitchContext(cond, Some(when(p)(block)), lits ++ newLits)
+//       }
+//     } else {
+//       this
+//     }
+//   }
+//   def is(v: T)(block: => Any)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SwitchContext[T] =
+//     is(Seq(v))(block)
+//   def is(
+//     v:     T,
+//     vr:    T*
+//   )(block: => Any
+//   )(
+//     implicit sourceInfo: SourceInfo,
+//     compileOptions:      CompileOptions
+//   ): SwitchContext[T] = is(v :: vr.toList)(block)
+// }
 
-/** Use to specify cases in a [[switch]] block, equivalent to a [[when$ when]] block comparing to
-  * the condition variable.
-  *
-  * @note illegal outside a [[switch]] block
-  * @note must be a literal
-  * @note each is must be mutually exclusive
-  * @note dummy implementation, a macro inside [[switch]] transforms this into the actual
-  * implementation
-  */
-object is {
-  // TODO: Begin deprecation of non-type-parameterized is statements.
-  /** Executes `block` if the switch condition is equal to any of the values in `v`.
-    */
-  def apply(v: Iterable[Element])(block: => Any) {
-    require(false, "The 'is' keyword may not be used outside of a switch.")
-  }
+// /** Use to specify cases in a [[switch]] block, equivalent to a [[when$ when]] block comparing to
+//   * the condition variable.
+//   *
+//   * @note illegal outside a [[switch]] block
+//   * @note must be a literal
+//   * @note each is must be mutually exclusive
+//   * @note dummy implementation, a macro inside [[switch]] transforms this into the actual
+//   * implementation
+//   */
+// object is {
+//   // TODO: Begin deprecation of non-type-parameterized is statements.
+//   /** Executes `block` if the switch condition is equal to any of the values in `v`.
+//     */
+//   def apply(v: Iterable[Element])(block: => Any) {
+//     require(false, "The 'is' keyword may not be used outside of a switch.")
+//   }
 
-  /** Executes `block` if the switch condition is equal to `v`.
-    */
-  def apply(v: Element)(block: => Any) {
-    require(false, "The 'is' keyword may not be used outside of a switch.")
-  }
+//   /** Executes `block` if the switch condition is equal to `v`.
+//     */
+//   def apply(v: Element)(block: => Any) {
+//     require(false, "The 'is' keyword may not be used outside of a switch.")
+//   }
 
-  /** Executes `block` if the switch condition is equal to any of the values in the argument list.
-    */
-  def apply(v: Element, vr: Element*)(block: => Any) {
-    require(false, "The 'is' keyword may not be used outside of a switch.")
-  }
-}
+//   /** Executes `block` if the switch condition is equal to any of the values in the argument list.
+//     */
+//   def apply(v: Element, vr: Element*)(block: => Any) {
+//     require(false, "The 'is' keyword may not be used outside of a switch.")
+//   }
+// }
 
-/** Conditional logic to form a switch block. See [[is$ is]] for the case API.
-  *
-  * @example {{{
-  * switch (myState) {
-  *   is (state1) {
-  *     // some logic here that runs when myState === state1
-  *   }
-  *   is (state2) {
-  *     // some logic here that runs when myState === state2
-  *   }
-  * }
-  * }}}
-  */
-object switch {
-  def apply[T <: Element](cond: T)(x: => Any): Unit = macro impl
-  def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = {
-    import c.universe._
-    val q"..$body" = x
-    val res = body.foldLeft(q"""new chisel3.util.SwitchContext($cond, None, Set.empty)""") {
-      case (acc, tree) =>
-        tree match {
-          // TODO: remove when Chisel compatibility package is removed
-          case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
-          case q"chisel3.util.is.apply( ..$params )( ..$body )"     => q"$acc.is( ..$params )( ..$body )"
-          case b                                                    => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
-        }
-    }
-    q"""{ $res }"""
-  }
-}
+// /** Conditional logic to form a switch block. See [[is$ is]] for the case API.
+//   *
+//   * @example {{{
+//   * switch (myState) {
+//   *   is (state1) {
+//   *     // some logic here that runs when myState === state1
+//   *   }
+//   *   is (state2) {
+//   *     // some logic here that runs when myState === state2
+//   *   }
+//   * }
+//   * }}}
+//   */
+// object switch {
+//   def apply[T <: Element](cond: T)(x: => Any): Unit = macro impl
+//   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = {
+//     import c.universe._
+//     val q"..$body" = x
+//     val res = body.foldLeft(q"""new chisel3.util.SwitchContext($cond, None, Set.empty)""") {
+//       case (acc, tree) =>
+//         tree match {
+//           // TODO: remove when Chisel compatibility package is removed
+//           case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
+//           case q"chisel3.util.is.apply( ..$params )( ..$body )"     => q"$acc.is( ..$params )( ..$body )"
+//           case b                                                    => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
+//         }
+//     }
+//     q"""{ $res }"""
+//   }
+// }
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index be6e3257..ba9466e1 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -55,7 +55,9 @@ class Counter private (r: Range, oldN: Option[Int] = None) extends AffectsChisel
     *
     * @param n number of steps before the counter resets
     */
-  def this(n: Int) { this(0 until math.max(1, n), Some(n)) }
+  def this(n: Int) = {
+    this(0 until math.max(1, n), Some(n))
+  }
 
   /** The current value of the counter. */
   val value = if (r.length > 1) RegInit(r.head.U(width.W)) else WireInit(r.head.U)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index f8c8f9e9..a0d86a75 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -22,7 +22,6 @@ import scala.annotation.nowarn
 abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: Module)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }
 
@@ -253,20 +252,12 @@ class Queue[T <: Data](
   val flow:           Boolean = false,
   val useSyncReadMem: Boolean = false,
   val hasFlush:       Boolean = false
-)(
-  implicit compileOptions: chisel3.CompileOptions)
-    extends Module() {
+) extends Module() {
   require(entries > -1, "Queue must have non-negative number of entries")
   require(entries != 0, "Use companion object Queue.apply for zero entries")
-  val genType = if (compileOptions.declaredTypeMustBeUnbound) {
+  val genType = {
     requireIsChiselType(gen)
     gen
-  } else {
-    if (DataMirror.internal.isSynthesizable(gen)) {
-      chiselTypeOf(gen)
-    } else {
-      gen
-    }
   }
 
   val io = IO(new QueueIO(genType, entries, hasFlush))
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala
index 5f8c9da8..5ea45fc5 100644
--- a/src/main/scala/chisel3/util/MixedVec.scala
+++ b/src/main/scala/chisel3/util/MixedVec.scala
@@ -89,9 +89,7 @@ object MixedVec {
   */
 final class MixedVec[T <: Data](private val eltsIn: Seq[T]) extends Record with collection.IndexedSeq[T] {
   // We want to create MixedVec only with Chisel types.
-  if (compileOptions.declaredTypeMustBeUnbound) {
-    eltsIn.foreach(e => requireIsChiselType(e))
-  }
+  eltsIn.foreach(e => requireIsChiselType(e))
 
   // In Scala 2.13, this is protected in IndexedSeq, must override as public because it's public in
   // Record
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index cb0e166a..71e6e050 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -119,7 +119,7 @@ object Pipe {
     * @return $returnType
     */
   @nowarn("cat=deprecation&msg=TransitName")
-  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = {
+  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
     require(latency >= 0, "Pipe latency must be greater than or equal to zero!")
     if (latency == 0) {
       val out = Wire(Valid(chiselTypeOf(enqBits)))
@@ -129,7 +129,7 @@ object Pipe {
     } else {
       val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
-      val out = apply(v, b, latency - 1)(compileOptions)
+      val out = apply(v, b, latency - 1)
 
       TransitName.withSuffix("Pipe_valid")(out, v)
       TransitName.withSuffix("Pipe_bits")(out, b)
@@ -141,8 +141,8 @@ object Pipe {
     * @param enqBits the data (must be a hardware type)
     * @return $returnType
     */
-  def apply[T <: Data](enqValid: Bool, enqBits: T)(implicit compileOptions: CompileOptions): Valid[T] = {
-    apply(enqValid, enqBits, 1)(compileOptions)
+  def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = {
+    apply(enqValid, enqBits, 1)
   }
 
   /** Generate a pipe for a [[Valid]] interface
@@ -150,8 +150,8 @@ object Pipe {
     * @param latency the number of pipeline stages
     * @return $returnType
     */
-  def apply[T <: Data](enq: Valid[T], latency: Int = 1)(implicit compileOptions: CompileOptions): Valid[T] = {
-    apply(enq.valid, enq.bits, latency)(compileOptions)
+  def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = {
+    apply(enq.valid, enq.bits, latency)
   }
 }
 
@@ -181,7 +181,7 @@ object Pipe {
   * @see [[Queue]] and the [[Queue$ Queue factory]] for actual queues
   * @see The [[ShiftRegister$ ShiftRegister factory]] to generate a pipe without a [[Valid]] interface
   */
-class Pipe[T <: Data](val gen: T, val latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module {
+class Pipe[T <: Data](val gen: T, val latency: Int = 1) extends Module {
 
   /** Interface for [[Pipe]]s composed of a [[Valid]] input and [[Valid]] output
     * @define notAQueue
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index bd46abe9..15c6ff6f 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -4,6 +4,7 @@ package chisel3.util.experimental
 
 import chisel3._
 import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.annotations._
 import firrtl.ir.{Module => _, _}
 import firrtl.transforms.BlackBoxInlineAnno
diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
index ce2da3c0..c5e9a5c3 100644
--- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala
@@ -7,6 +7,7 @@ import chisel3.experimental.{annotate, ChiselAnnotation}
 import chisel3.util.{pla, BitPat}
 import chisel3.util.experimental.{getAnnotations, BitSet}
 import chisel3.internal.Builder
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import firrtl.annotations.Annotation
 import logger.LazyLogging
 
diff --git a/src/main/scala/chisel3/util/experimental/group.scala b/src/main/scala/chisel3/util/experimental/group.scala
index 202c95d8..ac687da7 100644
--- a/src/main/scala/chisel3/util/experimental/group.scala
+++ b/src/main/scala/chisel3/util/experimental/group.scala
@@ -51,13 +51,9 @@ object group {
     newInstance:  String,
     outputSuffix: Option[String] = None,
     inputSuffix:  Option[String] = None
-  )(
-    implicit compileOptions: CompileOptions
   ): Unit = {
-    if (compileOptions.checkSynthesizable) {
-      components.foreach { data =>
-        requireIsHardware(data, s"Component ${data.toString} is marked to group, but is not bound.")
-      }
+    components.foreach { data =>
+      requireIsHardware(data, s"Component ${data.toString} is marked to group, but is not bound.")
     }
     annotate(new ChiselAnnotation with RunFirrtlTransform {
       def toFirrtl = GroupAnnotation(components.map(_.toNamed), newModule, newInstance, outputSuffix, inputSuffix)
diff --git a/src/main/scala/chisel3/util/util.scala b/src/main/scala/chisel3/util/util.scala
index 6ea1f629..04f6ab6c 100644
--- a/src/main/scala/chisel3/util/util.scala
+++ b/src/main/scala/chisel3/util/util.scala
@@ -10,5 +10,5 @@ package object util {
   /** Synonyms, moved from main package object - maintain scope. */
   type ValidIO[+T <: Data] = chisel3.util.Valid[T]
   val ValidIO = chisel3.util.Valid
-  val DecoupledIO = chisel3.util.Decoupled
+  // val DecoupledIO = chisel3.util.Decoupled
 }