diff options
| author | Jim Lawson | 2016-07-25 14:06:51 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-25 17:07:33 -0700 |
| commit | 7aa05590382b0528799ad5e9f1318ce42e409793 (patch) | |
| tree | 9af7c7513f60efa30c59172a234a8f2926b5430f /src/main/scala/chisel3/util/CircuitMath.scala | |
| parent | 3624751e2e63ba9f107c795529edfe48cf8340b2 (diff) | |
Minimize differences with master.
Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.
Diffstat (limited to 'src/main/scala/chisel3/util/CircuitMath.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/CircuitMath.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index 27bd7bfb..c809e14b 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -16,11 +16,11 @@ object Log2 { /** Compute the Log2 on the least significant n bits of x */ def apply(x: Bits, width: Int): UInt = { if (width < 2) { - UInt.Lit(0) + UInt(0) } else if (width == 2) { x(1) } else if (width <= divideAndConquerThreshold) { - Mux(x(width-1), UInt.Lit(width-1), apply(x, width-1)) + Mux(x(width-1), UInt(width-1), apply(x, width-1)) } else { val mid = 1 << (log2Ceil(width) - 1) val hi = x(width-1, mid) |