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authorJack Koenig2016-12-21 14:33:07 -0800
committerJack Koenig2017-02-08 18:00:32 -0800
commit66a72ff64c46d8a9fdade77223de62b4dcfe2825 (patch)
tree8ff97057072ed7ec1e1c64b3f1db774e2c09f99e /src/main/scala/chisel3/package.scala
parent132b80edee2fb8e730d3b6f5eb5f36051a819525 (diff)
Add Analog type
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
Diffstat (limited to 'src/main/scala/chisel3/package.scala')
-rw-r--r--src/main/scala/chisel3/package.scala4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index a5d782ea..a236d3da 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -264,6 +264,10 @@ package object chisel3 { // scalastyle:ignore package.object.name
type RawParam = chisel3.core.RawParam
val RawParam = chisel3.core.RawParam
+ type Analog = chisel3.core.Analog
+ val Analog = chisel3.core.Analog
+ val attach = chisel3.core.attach
+
// Implicit conversions for BlackBox Parameters
implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x))
implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x))