From 66a72ff64c46d8a9fdade77223de62b4dcfe2825 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 21 Dec 2016 14:33:07 -0800
Subject: Add Analog type

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
---
 src/main/scala/chisel3/package.scala | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/main/scala/chisel3/package.scala')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index a5d782ea..a236d3da 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -264,6 +264,10 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     type RawParam = chisel3.core.RawParam
     val RawParam = chisel3.core.RawParam
 
+    type Analog = chisel3.core.Analog
+    val Analog = chisel3.core.Analog
+    val attach = chisel3.core.attach
+
     // Implicit conversions for BlackBox Parameters
     implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x))
     implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x))
-- 
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