diff options
| author | Albert Magyar | 2020-07-20 12:11:44 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-07-21 13:06:53 -0700 |
| commit | 7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 (patch) | |
| tree | 1fa15e357d0af7b82316fa2ee659e2e98118488c /src/main/scala/chisel3/internal | |
| parent | 4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff) | |
Delete outdated scalastyle configuration comments from source
Diffstat (limited to 'src/main/scala/chisel3/internal')
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 2124fa25..be8d8f2f 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -25,7 +25,7 @@ private class Emitter(circuit: Circuit) { s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}" } - private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit + private def emitType(d: Data, clearDir: Boolean = false): String = d match { case d: Clock => "Clock" case _: AsyncReset => "AsyncReset" case _: ResetType => "Reset" @@ -62,15 +62,15 @@ private class Emitter(circuit: Circuit) { case d => d.specifiedDirection } - private def emit(e: Command, ctx: Component): String = { // scalastyle:ignore cyclomatic.complexity + private def emit(e: Command, ctx: Component): String = { val firrtlLine = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}" case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}" - case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit + case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}" - case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit + case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")") @@ -101,7 +101,6 @@ private class Emitter(circuit: Circuit) { s"skip" } firrtlLine + e.sourceInfo.makeMessage(" " + _) - // scalastyle:on line.size.limit } private def emitParam(name: String, p: Param): String = { |