diff options
| author | Albert Magyar | 2020-02-03 13:42:39 -0700 |
|---|---|---|
| committer | GitHub | 2020-02-03 13:42:39 -0700 |
| commit | 509895c428f73b1c47e018df33e6cb64834e6e94 (patch) | |
| tree | e2912c1c7528df820fe9163272397edd7efa1259 /src/main/scala/chisel3/internal | |
| parent | 4f1f638663a7176ac28d95d71c14a37021314c3b (diff) | |
Add read-under-write parameter to SyncReadMem (#1183)
* Add support for readUnderWrite to SyncReadMem
* Add write collision behavior test to MemorySpec
* Update constant names
Diffstat (limited to 'src/main/scala/chisel3/internal')
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 3409ce94..1341b5f6 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -69,7 +69,7 @@ private class Emitter(circuit: Circuit) { case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}" case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]" - case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}]" + case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}" case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" |