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authorducky2016-05-20 18:09:57 -0700
committerducky2016-06-08 16:22:27 -0700
commitf36524e388b060b1bb535ae21cb1bcbbea220be9 (patch)
treea32772f816f18b14002948964917be0cb8280c48 /src/main/scala/chisel/util/OneHot.scala
parent53813f61b7dfe246d214ab966739d01c65c8ecb0 (diff)
Rename packages to lowercase chisel, add compatibility layer
Diffstat (limited to 'src/main/scala/chisel/util/OneHot.scala')
-rw-r--r--src/main/scala/chisel/util/OneHot.scala62
1 files changed, 62 insertions, 0 deletions
diff --git a/src/main/scala/chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala
new file mode 100644
index 00000000..5d1de1a7
--- /dev/null
+++ b/src/main/scala/chisel/util/OneHot.scala
@@ -0,0 +1,62 @@
+// See LICENSE for license details.
+
+/** Circuit generators for working with one-hot representations.
+ */
+
+package chisel
+
+/** Converts from One Hot Encoding to a UInt indicating which bit is active
+ * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
+object OHToUInt {
+ def apply(in: Seq[Bool]): UInt = apply(Vec(in))
+ def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size)
+ def apply(in: Bits): UInt = apply(in, in.getWidth)
+
+ def apply(in: Bits, width: Int): UInt = {
+ if (width <= 2) {
+ Log2(in, width)
+ } else {
+ val mid = 1 << (log2Up(width)-1)
+ val hi = in(width-1, mid)
+ val lo = in(mid-1, 0)
+ Cat(hi.orR, apply(hi | lo, mid))
+ }
+ }
+}
+
+/** @return the bit position of the trailing 1 in the input vector
+ * with the assumption that multiple bits of the input bit vector can be set
+ * @example {{{ data_out := PriorityEncoder(data_in) }}}
+ */
+object PriorityEncoder {
+ def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+ def apply(in: Bits): UInt = apply(in.toBools)
+}
+
+/** Returns the one hot encoding of the input UInt.
+ */
+object UIntToOH
+{
+ def apply(in: UInt, width: Int = -1): UInt =
+ if (width == -1) {
+ UInt(1) << in
+ } else {
+ (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+ }
+}
+
+/** Returns a bit vector in which only the least-significant 1 bit in
+ the input vector, if any, is set.
+ */
+object PriorityEncoderOH
+{
+ private def encode(in: Seq[Bool]): UInt = {
+ val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size))
+ PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size))
+ }
+ def apply(in: Seq[Bool]): Seq[Bool] = {
+ val enc = encode(in)
+ Seq.tabulate(in.size)(enc(_))
+ }
+ def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i)))
+}