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authorAndrew Waterman2016-03-31 15:35:33 -0700
committerAndrew Waterman2016-04-01 16:34:47 -0700
commit70062576bc609b436ae09320565b6ccfa5deb123 (patch)
treeff2be0060b6ec7b75637fc5f878b550b58a47a5a /src/main/scala/Chisel
parent08ec6f037c2fd301624d815b85942ebc24152a87 (diff)
Reduce FIRRTL node count for Counter
This would ultimately get DCE'd, but it's easy enough to not generate the dead code in the first place.
Diffstat (limited to 'src/main/scala/Chisel')
-rw-r--r--src/main/scala/Chisel/util/Counter.scala4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/Chisel/util/Counter.scala
index 3425b6a2..14f51ec4 100644
--- a/src/main/scala/Chisel/util/Counter.scala
+++ b/src/main/scala/Chisel/util/Counter.scala
@@ -17,7 +17,9 @@ class Counter(val n: Int) {
Bool(true)
} else {
val wrap = value === UInt(n-1)
- value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1))
+ value := value + UInt(1)
+ if (!isPow2(n))
+ when (wrap) { value := UInt(0) }
wrap
}
}