diff options
| author | Andrew Waterman | 2016-03-31 15:35:33 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-04-01 16:34:47 -0700 |
| commit | 70062576bc609b436ae09320565b6ccfa5deb123 (patch) | |
| tree | ff2be0060b6ec7b75637fc5f878b550b58a47a5a | |
| parent | 08ec6f037c2fd301624d815b85942ebc24152a87 (diff) | |
Reduce FIRRTL node count for Counter
This would ultimately get DCE'd, but it's easy enough to not
generate the dead code in the first place.
| -rw-r--r-- | src/main/scala/Chisel/util/Counter.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/Chisel/util/Counter.scala index 3425b6a2..14f51ec4 100644 --- a/src/main/scala/Chisel/util/Counter.scala +++ b/src/main/scala/Chisel/util/Counter.scala @@ -17,7 +17,9 @@ class Counter(val n: Int) { Bool(true) } else { val wrap = value === UInt(n-1) - value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1)) + value := value + UInt(1) + if (!isPow2(n)) + when (wrap) { value := UInt(0) } wrap } } |
