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authorducky2016-05-20 18:09:57 -0700
committerducky2016-06-08 16:22:27 -0700
commitf36524e388b060b1bb535ae21cb1bcbbea220be9 (patch)
treea32772f816f18b14002948964917be0cb8280c48 /src/main/scala/Chisel/util/CircuitMath.scala
parent53813f61b7dfe246d214ab966739d01c65c8ecb0 (diff)
Rename packages to lowercase chisel, add compatibility layer
Diffstat (limited to 'src/main/scala/Chisel/util/CircuitMath.scala')
-rw-r--r--src/main/scala/Chisel/util/CircuitMath.scala26
1 files changed, 0 insertions, 26 deletions
diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/Chisel/util/CircuitMath.scala
deleted file mode 100644
index 06cab903..00000000
--- a/src/main/scala/Chisel/util/CircuitMath.scala
+++ /dev/null
@@ -1,26 +0,0 @@
-// See LICENSE for license details.
-
-/** Circuit-land math operations.
- */
-
-package Chisel
-
-/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
- * An alternative interpretation is it computes the minimum number of bits needed to represent x
- * @example
- * {{{ data_out := Log2(data_in) }}}
- * @note Truncation is used so Log2(UInt(12412)) = 13*/
-object Log2 {
- /** Compute the Log2 on the least significant n bits of x */
- def apply(x: Bits, width: Int): UInt = {
- if (width < 2) {
- UInt(0)
- } else if (width == 2) {
- x(1)
- } else {
- Mux(x(width-1), UInt(width-1), apply(x, width-1))
- }
- }
-
- def apply(x: Bits): UInt = apply(x, x.getWidth)
-}