diff options
| author | jackkoenig | 2016-05-20 13:38:18 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-20 13:38:18 -0700 |
| commit | d7697eb14a0195cc3726bf45fdf38c631b6f6507 (patch) | |
| tree | 7b9372829fd9167e6d15d7f5323f6dfd4e5b11f4 /src/main/scala/Chisel/testers | |
| parent | a26a0ad4504e99182e3548db8f407c3dad7302b0 (diff) | |
Update BackendCompilationUtilities.verilogToCpp to specify top-module
This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
Diffstat (limited to 'src/main/scala/Chisel/testers')
| -rw-r--r-- | src/main/scala/Chisel/testers/TesterDriver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index c0cdfb3f..a56bb8b7 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -47,7 +47,7 @@ object TesterDriver extends BackendCompilationUtilities { // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe if ((firrtlToVerilog(target, path) #&& - verilogToCpp(target, path, additionalVFiles, cppHarness) #&& + verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& cppToExe(target, path)).! == 0) { executeExpectingSuccess(target, path) } else { |