From d7697eb14a0195cc3726bf45fdf38c631b6f6507 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Fri, 20 May 2016 13:38:18 -0700
Subject: Update BackendCompilationUtilities.verilogToCpp to specify top-module

This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
---
 src/main/scala/Chisel/testers/TesterDriver.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/Chisel/testers')

diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
index c0cdfb3f..a56bb8b7 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -47,7 +47,7 @@ object TesterDriver extends BackendCompilationUtilities {
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
     if ((firrtlToVerilog(target, path) #&&
-        verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+        verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
         cppToExe(target, path)).! == 0) {
       executeExpectingSuccess(target, path)
     } else {
-- 
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