diff options
| author | ducky | 2015-12-09 14:18:46 -0800 |
|---|---|---|
| committer | ducky | 2015-12-09 14:46:06 -0800 |
| commit | cd016b42a0c940f671bdd3c117b8f0ae3c4b30b5 (patch) | |
| tree | 4c54d1322e2464a0e5c2e25d03cb34b5f21e239f /src/main/scala/Chisel/testers | |
| parent | 035a30d25cdd955af6385c1334826781b17d894c (diff) | |
Extend TesterDriver to optionally take in additional Verilog sources
Diffstat (limited to 'src/main/scala/Chisel/testers')
| -rw-r--r-- | src/main/scala/Chisel/testers/TesterDriver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index d104782a..4c6134f0 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -29,7 +29,7 @@ object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe if (((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&& firrtlToVerilog(prefix, dir) #&& - verilogToCpp(prefix, dir, vDut, cppHarness, vH) #&& + verilogToCpp(prefix, dir, vDut, Seq(), cppHarness, vH) #&& cppToExe(prefix, dir)).! == 0) { executeExpectingSuccess(prefix, dir) } else { |
