Fix new style errors

2 files changed, 5 insertions, 3 deletions

diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala
index dbb269bb..398e49e7 100644
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ b/src/main/scala/Chisel/testers/BasicTester.scala
@@ -11,5 +11,5 @@ class BasicTester extends Module {
   io.done := Bool(false)
   io.error := UInt(0)
 
-  def popCount(n: Long) = n.toBinaryString.count(_=='1')
+  def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
 }
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
index 657f7d37..d104782a 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -27,11 +27,13 @@ object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities
     Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if(((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&&
+    if (((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&&
         firrtlToVerilog(prefix, dir) #&&
         verilogToCpp(prefix, dir, vDut, cppHarness, vH) #&&
         cppToExe(prefix, dir)).! == 0) {
       executeExpectingSuccess(prefix, dir)
-    } else false
+    } else {
+      false
+    }
   }
 }