Remove Parameters library and refactor Driver.

In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances,
this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester.

The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed.
Further work is needed on individual tests to use assertions instead of .io.error.

3 files changed, 39 insertions, 21 deletions

diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala
index c73567c4..dbb269bb 100644
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ b/src/main/scala/Chisel/testers/BasicTester.scala
@@ -10,4 +10,6 @@ class BasicTester extends Module {
   }
   io.done := Bool(false)
   io.error := UInt(0)
+
+  def popCount(n: Long) = n.toBinaryString.count(_=='1')
 }
diff --git a/src/main/scala/Chisel/testers/Driver.scala b/src/main/scala/Chisel/testers/Driver.scala
deleted file mode 100644
index 860ef69c..00000000
--- a/src/main/scala/Chisel/testers/Driver.scala
+++ /dev/null
@@ -1,21 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.testers
-import Chisel._
-
-object TesterDriver {
-  /** For use with modules that should successfully be elaborated by the
-    * frontend, and which can be turned into executeables with error codes. */
-  def execute(t: => BasicTester): Boolean = {
-    val circuit = Builder.build(Module(t))
-    //val executable = invokeFIRRTL(circuit)
-    //Process(executable) !
-    true
-  }
-
-  /** For use with modules that should illicit errors from the frontend
-    * or which produce IR with consistantly checkable properties. */
-  def elaborate(t: => Module): Circuit = {
-    Builder.build(Module(t))
-  }
-}
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
new file mode 100644
index 00000000..657f7d37
--- /dev/null
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -0,0 +1,37 @@
+// See LICENSE for license details.
+
+package Chisel.testers
+import Chisel._
+import scala.sys.process._
+import java.io.File
+
+object TesterDriver extends BackendCompilationUtilities with FileSystemUtilities {
+  /** For use with modules that should successfully be elaborated by the
+    * frontend, and which can be turned into executeables with assertions. */
+  def execute(t: () => BasicTester): Boolean = {
+    // Invoke the chisel compiler to get the circuit's IR
+    val circuit = Driver.elaborate(t)
+
+    // Set up a bunch of file handlers based on a random temp filename,
+    // plus the quirks of Verilator's naming conventions
+    val target = circuit.name
+    val fname = File.createTempFile(target, "")
+    val path = fname.getParentFile.toString
+    val prefix = fname.toString.split("/").last
+    val dir = new File(System.getProperty("java.io.tmpdir"))
+    val vDut = new File(fname.toString + ".v")
+    val vH = new File(path + "/V" + prefix + ".h")
+    val cppHarness = new File(fname.toString + ".cpp")
+
+    // For now, dump the IR out to a file
+    Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
+
+    // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
+    if(((new File(System.getProperty("user.dir") + "/src/main/resources/top.cpp") #> cppHarness) #&&
+        firrtlToVerilog(prefix, dir) #&&
+        verilogToCpp(prefix, dir, vDut, cppHarness, vH) #&&
+        cppToExe(prefix, dir)).! == 0) {
+      executeExpectingSuccess(prefix, dir)
+    } else false
+  }
+}