diff options
| author | Andrew Waterman | 2016-01-27 15:20:58 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-27 15:20:58 -0800 |
| commit | bce4a96934fe8575b71769f2e52a2b75a068d34d (patch) | |
| tree | 3f28593b8f4b7e9d5642d1dab76bee12db38834c /src/main/scala/Chisel/internal | |
| parent | c9dd94dd6968cba5ecd44fee6df3071cb7a25a9c (diff) | |
Use FIRRTL nodes add+tail instead of addw
Diffstat (limited to 'src/main/scala/Chisel/internal')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index cc80e3aa..3e923366 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -10,9 +10,9 @@ case class PrimOp(val name: String) { object PrimOp { val AddOp = PrimOp("add") - val AddModOp = PrimOp("addw") val SubOp = PrimOp("sub") - val SubModOp = PrimOp("subw") + val TailOp = PrimOp("tail") + val HeadOp = PrimOp("head") val TimesOp = PrimOp("mul") val DivideOp = PrimOp("div") val RemOp = PrimOp("rem") |