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| author | Andrew Waterman | 2016-01-27 15:20:44 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-27 15:20:44 -0800 |
| commit | c9dd94dd6968cba5ecd44fee6df3071cb7a25a9c (patch) | |
| tree | cc11c932be7a854ffe8e28fefe929042a0f41918 /src/main/scala/Chisel/internal | |
| parent | 22d302ad066d8a073e44289ba4876a165ea56b05 (diff) | |
Use FIRRTL node rem, not mod, for %
Diffstat (limited to 'src/main/scala/Chisel/internal')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index 1bc3ad89..cc80e3aa 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -15,7 +15,7 @@ object PrimOp { val SubModOp = PrimOp("subw") val TimesOp = PrimOp("mul") val DivideOp = PrimOp("div") - val ModOp = PrimOp("mod") + val RemOp = PrimOp("rem") val ShiftLeftOp = PrimOp("shl") val ShiftRightOp = PrimOp("shr") val DynamicShiftLeftOp = PrimOp("dshl") |