From bce4a96934fe8575b71769f2e52a2b75a068d34d Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:58 -0800
Subject: Use FIRRTL nodes add+tail instead of addw

---
 src/main/scala/Chisel/internal/firrtl/IR.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/main/scala/Chisel/internal')

diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index cc80e3aa..3e923366 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -10,9 +10,9 @@ case class PrimOp(val name: String) {
 
 object PrimOp {
   val AddOp = PrimOp("add")
-  val AddModOp = PrimOp("addw")
   val SubOp = PrimOp("sub")
-  val SubModOp = PrimOp("subw")
+  val TailOp = PrimOp("tail")
+  val HeadOp = PrimOp("head")
   val TimesOp = PrimOp("mul")
   val DivideOp = PrimOp("div")
   val RemOp = PrimOp("rem")
-- 
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