diff options
| author | Andrew Waterman | 2016-04-14 17:42:18 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-04-14 22:58:51 -0700 |
| commit | 3506c54b87abfd6e0269effb4685a58c881a890e (patch) | |
| tree | e82a5244efa0bfe7484e6e24d33f6e33282c47ff /src/main/scala/Chisel/Module.scala | |
| parent | a55309514ef9a89e5c830b1f1fe6d9719e986422 (diff) | |
Eliminate RefMap
It's an unconvincing means to pretend there isn't mutable state when
there really is. It's more confusing and less performant than just
calling a spade a spade.
Diffstat (limited to 'src/main/scala/Chisel/Module.scala')
| -rw-r--r-- | src/main/scala/Chisel/Module.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala index 463c2f81..22c1f9c3 100644 --- a/src/main/scala/Chisel/Module.scala +++ b/src/main/scala/Chisel/Module.scala @@ -53,8 +53,6 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId { val reset = Bool(INPUT) private[Chisel] def addId(d: HasId) { _ids += d } - private[Chisel] def ref = Builder.globalRefMap(this) - private[Chisel] def lref = ref private def ports = (clock, "clk") :: (reset, "reset") :: (io, "io") :: Nil |