diff options
| author | Andrew Waterman | 2015-08-28 15:03:21 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-08-28 15:03:21 -0700 |
| commit | 3c7a3ca3a85e59c64515b8f3b90c77fd463f42bf (patch) | |
| tree | 6436fbdbe97884a4d3d25e32d4c8b0983fbe7eba /src/main/scala/Chisel/IR.scala | |
| parent | f455315b5dbcda826d7d1a1fdb31b524621c6225 (diff) | |
Use FIRRTL smem for SeqMem
Read enables and read-write ports aren't working yet.
Diffstat (limited to 'src/main/scala/Chisel/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/IR.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 35211184..90ca349c 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -142,8 +142,8 @@ case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition case class DefWire(id: Data) extends Definition case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition -case class DefSeqMemory(id: Data, size: Int) extends Definition -case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition +case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition +case class DefAccessor[T <: Data](id: T, source: Alias, direction: Direction, index: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Port]) extends Definition case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command |