Use FIRRTL smem for SeqMem

Read enables and read-write ports aren't working yet.

3 files changed, 18 insertions, 23 deletions

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index ee322ac5..8f1b6b14 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -142,38 +142,33 @@ object Mem {
   }
 }
 
-sealed class Mem[T <: Data](t: T, val length: Int) extends HasId with VecLike[T] {
+sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId with VecLike[T] {
   def apply(idx: Int): T = apply(UInt(idx))
-  def apply(idx: UInt): T = {
-    val x = t.cloneType
-    pushCommand(DefAccessor(x, Alias(this), NO_DIR, idx.ref))
-    x
-  }
+  def apply(idx: UInt): T =
+    pushCommand(DefAccessor(t.cloneType, Alias(this), NO_DIR, idx.ref)).id
 
   def read(idx: UInt): T = apply(idx)
   def write(idx: UInt, data: T): Unit = apply(idx) := data
   def write(idx: UInt, data: T, mask: Vec[Bool]) (implicit evidence: T <:< Vec[_]): Unit = {
-    val accessor = this.asInstanceOf[Mem[Vec[Data]]].apply(idx)
+    val accessor = apply(idx).asInstanceOf[Vec[Data]]
     for (((cond, port), datum) <- mask zip accessor zip data.asInstanceOf[Vec[Data]])
       when (cond) { port := datum }
   }
 }
 
+sealed class Mem[T <: Data](t: T, length: Int) extends MemBase(t, length)
+
 object SeqMem {
-  def apply[T <: Data](t: T, size: Int): SeqMem[T] =
-    new SeqMem(t, size)
+  def apply[T <: Data](t: T, size: Int): SeqMem[T] = {
+    val mt  = t.cloneType
+    val mem = new SeqMem(mt, size)
+    pushCommand(DefSeqMemory(mem, mt, size, Alias(mt._parent.get.clock))) // TODO multi-clock
+    mem
+  }
 }
 
-// For now, implement SeqMem in terms of Mem
-sealed class SeqMem[T <: Data](t: T, n: Int) {
-  private val mem = Mem(t, n)
-
-  def read(addr: UInt): T = mem.read(Reg(next = addr))
-  def read(addr: UInt, enable: Bool): T = mem.read(RegEnable(addr, enable))
-
-  def write(addr: UInt, data: T): Unit = mem.write(addr, data)
-  def write(addr: UInt, data: T, mask: Vec[Bool]) (implicit evidence: T <:< Vec[_]): Unit =
-    mem.write(addr, data, mask)
+sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
+  def read(addr: UInt, enable: Bool): T = read(addr) // TODO read enable
 }
 
 object Vec {
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index 643135b1..b10b477e 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -11,8 +11,8 @@ private class Emitter(circuit: Circuit) {
     case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
     case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
     case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
-    case e: DefSeqMemory => s"smem ${e.name} : ${e.id.toType}[${e.size}]";
-    case e: DefAccessor => s"infer accessor ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}]"
+    case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
+    case e: DefAccessor[_] => s"infer accessor ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}]"
     case e: Connect => s"${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
     case e: BulkConnect => s"${e.loc1.fullName(ctx)} <> ${e.loc2.fullName(ctx)}"
     case e: ConnectInit => s"onreset ${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 35211184..90ca349c 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -142,8 +142,8 @@ case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefWire(id: Data) extends Definition
 case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition
 case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
-case class DefSeqMemory(id: Data, size: Int) extends Definition
-case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition
+case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
+case class DefAccessor[T <: Data](id: T, source: Alias, direction: Direction, index: Arg) extends Definition
 case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
 case class DefPoison[T <: Data](id: T) extends Definition
 case class WhenBegin(pred: Arg) extends Command