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Diffstat (limited to 'src/main/scala/Chisel/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/IR.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 35211184..90ca349c 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -142,8 +142,8 @@ case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition case class DefWire(id: Data) extends Definition case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition -case class DefSeqMemory(id: Data, size: Int) extends Definition -case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition +case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition +case class DefAccessor[T <: Data](id: T, source: Alias, direction: Direction, index: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Port]) extends Definition case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command |