Merge pull request #1384 from freechipsproject/no-more-compile-internal

No more compile internal

1 files changed, 25 insertions, 0 deletions

diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala
new file mode 100644
index 00000000..c1c6b1db
--- /dev/null
+++ b/core/src/main/scala/chisel3/SIntFactory.scala
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.internal.firrtl.{IntervalRange, SLit, Width}
+
+trait SIntFactory {
+  /** Create an SInt type with inferred width. */
+  def apply(): SInt = apply(Width())
+  /** Create a SInt type or port with fixed width. */
+  def apply(width: Width): SInt = new SInt(width)
+
+  /** Create a SInt with the specified range */
+  def apply(range: IntervalRange): SInt = {
+    apply(range.getWidth)
+  }
+
+  /** Create an SInt literal with specified width. */
+  // scalastyle:off method.name
+  protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
+    val lit = SLit(value, width)
+    val result = new SInt(lit.width)
+    lit.bindLitArg(result)
+  }
+}