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authorJack Koenig2020-03-22 18:13:58 -0700
committerJack Koenig2020-03-25 19:17:15 -0700
commitfbf5e6f1a0e8bf535d465b748ad554575fe62156 (patch)
tree578858ab6d219ca6daf44cf87b73f75054989097 /core/src/main/scala/chisel3/SIntFactory.scala
parentb2e004fb615a3c931d910a338b9faa99c1c975d7 (diff)
Rename subprojects to more canonical names
* Rename coreMacros to macros * Rename chiselFrontend to core Also make each subproject publish with "chisel3-" as a prefix
Diffstat (limited to 'core/src/main/scala/chisel3/SIntFactory.scala')
-rw-r--r--core/src/main/scala/chisel3/SIntFactory.scala25
1 files changed, 25 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala
new file mode 100644
index 00000000..c1c6b1db
--- /dev/null
+++ b/core/src/main/scala/chisel3/SIntFactory.scala
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.internal.firrtl.{IntervalRange, SLit, Width}
+
+trait SIntFactory {
+ /** Create an SInt type with inferred width. */
+ def apply(): SInt = apply(Width())
+ /** Create a SInt type or port with fixed width. */
+ def apply(width: Width): SInt = new SInt(width)
+
+ /** Create a SInt with the specified range */
+ def apply(range: IntervalRange): SInt = {
+ apply(range.getWidth)
+ }
+
+ /** Create an SInt literal with specified width. */
+ // scalastyle:off method.name
+ protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
+ val lit = SLit(value, width)
+ val result = new SInt(lit.width)
+ lit.bindLitArg(result)
+ }
+}