diff options
| author | chick | 2016-06-06 15:03:36 -0700 |
|---|---|---|
| committer | chick | 2016-06-06 15:03:36 -0700 |
| commit | e98f9656591925464c42db70641d3cfa501f108a (patch) | |
| tree | 43b5f9464d9ccc19382b20dfff2a6d4b6ef6a826 /chiselFrontend | |
| parent | dc2175b0ebafbbb4b67bcb1e9b92b639b02b36bb (diff) | |
Changed deprecation warning for Data#toBits to recommend asUInt instead because the sole remaining use of toBits in chiselTests was to compare to Vectors declared differently but with same underlying bits.
Making at toBits was problematic because it did not support === method.
Changed Vec and Bundle to both support toUInt()
Note: If toBits is actually needed now, one can use toInt().toBits()
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 11 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Data.scala | 4 |
2 files changed, 14 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 1eef5d69..8af4e9e9 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -167,6 +167,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) + /** Reinterpret cast to UInt. */ + def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() + for ((elt, i) <- self zipWithIndex) elt.setRef(this, i) } @@ -341,6 +346,12 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten) private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt + + /** Reinterpret cast to UInt. */ + def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() + private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) } diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala index d16843f7..adb4ff7b 100644 --- a/chiselFrontend/src/main/scala/Chisel/Data.scala +++ b/chiselFrontend/src/main/scala/Chisel/Data.scala @@ -117,8 +117,10 @@ abstract class Data(dirArg: Direction) extends HasId { * * This performs the inverse operation of fromBits(Bits). */ - @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3") + @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3") def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo) + +// def asBits(): Bits } object Wire { |
