diff options
Diffstat (limited to 'chiselFrontend/src/main/scala/Chisel/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 1eef5d69..8af4e9e9 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -167,6 +167,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) + /** Reinterpret cast to UInt. */ + def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() + for ((elt, i) <- self zipWithIndex) elt.setRef(this, i) } @@ -341,6 +346,12 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten) private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt + + /** Reinterpret cast to UInt. */ + def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() + private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) } |
