diff options
| author | Richard Lin | 2018-05-24 11:54:37 -0700 |
|---|---|---|
| committer | Richard Lin | 2018-07-04 18:39:28 -0500 |
| commit | b4e76215634413ad39db47b7cbec87fc81e14e31 (patch) | |
| tree | 33f47e2216fe69741289856abea9b7fb28611dee /chiselFrontend | |
| parent | c2cd91f379015f4e56c321d9ab9e263a52dea5de (diff) | |
Comment out assertion test, fix ref generation
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 0550a72c..adf97dbe 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -95,7 +95,11 @@ sealed abstract class Bits(width: Width) // provide bits-specific literal handling functionality here override private[chisel3] def ref: Arg = topBindingOpt match { - case Some(binding: LitBinding) => binding.asInstanceOf[ElementLitBinding].litArg + case Some(ElementLitBinding(litArg)) => litArg + case Some(BundleLitBinding(litMap)) => litMap.get(this) match { + case Some(litArg) => litArg + case _ => throwException(s"internal error: DontCare should be caught before connect") + } case _ => super.ref } |
